component
SM74HC595D
Public Made by Adomby adom
Shenzhen Sunmoon Micro Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sm74hc595d",+ "title": "SM74HC595D",+ "brief": "Shenzhen Sunmoon Micro Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Shenzhen Sunmoon Micro Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sm74hc595d" ],+ "component": {+ "mpn": "SM74HC595D",+ "manufacturer": "Shenzhen Sunmoon Micro",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shifting Register",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/60b63267e84d48edb15919eee5d46019.pdf",+ "parts": {+ "symbol": "sm74hc595d.kicad_sym",+ "footprint": "sm74hc595d.kicad_mod",+ "model_3d": "sm74hc595d.glb",+ "model_3d_step": "sm74hc595d.step",+ "lbr": "sm74hc595d.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Q1",+ "type": "tri_state",+ "description": "Parallel latched output bit 1 from the storage register. Three-state; enabled when /G (pin 13) is low."+ },+ {+ "number": "2",+ "name": "Q2",+ "type": "tri_state",+ "description": "Parallel latched output bit 2. Three-state, enabled by /G low."+ },+ {+ "number": "3",+ "name": "Q3",+ "type": "tri_state",+ "description": "Parallel latched output bit 3. Three-state, enabled by /G low."+ },+ {+ "number": "4",+ "name": "Q4",+ "type": "tri_state",+ "description": "Parallel latched output bit 4. Three-state, enabled by /G low."+ },+ {+ "number": "5",+ "name": "Q5",+ "type": "tri_state",+ "description": "Parallel latched output bit 5. Three-state, enabled by /G low."+ },+ {+ "number": "6",+ "name": "Q6",+ "type": "tri_state",+ "description": "Parallel latched output bit 6. Three-state, enabled by /G low."+ },+ {+ "number": "7",+ "name": "Q7",+ "type": "tri_state",+ "description": "Parallel latched output bit 7 (MSB of the 8-bit output). Three-state, enabled by /G low."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Logic ground reference (0 V)."+ },+ {+ "number": "9",+ "name": "Q7'",+ "type": "output",+ "description": "Serial data output from the last stage of the shift register. Used to daisy-chain multiple 74HC595 devices; not three-state."+ },+ {+ "number": "10",+ "name": "/SCLR",+ "type": "input",+ "description": "Active-low asynchronous shift-register clear. Driving low forces all shift-register bits to 0 (Q7' = 0); does not affect the storage latch until an RCK edge."+ },+ {+ "number": "11",+ "name": "SCK",+ "type": "input",+ "description": "Shift-register clock. Data on SER is shifted into the shift register on the rising edge. Max 50 MHz (typ. 52 MHz at Vcc = 4.5 V)."+ },+ {+ "number": "12",+ "name": "RCK",+ "type": "input",+ "description": "Storage/latch register clock. On the rising edge, the shift-register contents are transferred to the output storage register (latched to Q0-Q7)."+ },+ {+ "number": "13",+ "name": "/G",+ "type": "input",+ "description": "Active-low output enable for the parallel outputs Q0-Q7. Low enables the latched data onto the outputs; high places Q0-Q7 in high-impedance (3-state)."+ },+ {+ "number": "14",+ "name": "SER",+ "type": "input",+ "description": "Serial data input to the shift register. Sampled on the rising edge of SCK; tSU \u2248 16 ns, tH \u2248 3 ns."+ },+ {+ "number": "15",+ "name": "Q0",+ "type": "tri_state",+ "description": "Parallel latched output bit 0 (LSB of the 8-bit output). Three-state, enabled by /G low."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2.0 V to 6.0 V. Bypass with 100 nF near the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/60b63267e84d48edb15919eee5d46019.pdf",+ "pages": 7,+ "sha256": "a82a24e37bce2202",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Shenzhen Sunmoon Micro",+ "Package": "SOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sm74hc595d"+ ],+ "discovery_pitch": "SM74HC595D (Shenzhen Sunmoon Micro) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/sm74hc595d-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }