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Set visibility: public

Ray ·f7e0dcbdda · ·parent 41bc7ee
1 file changed +10−7
page.json+10−7
@@ -38,13 +38,13 @@         "number": "2",         "name": "VMP",         "type": "input",-        "description": "Voltage sense terminal between VC1 and VMP, used as the overcurrent-3 (charger over-current / charger-detect) detection input. Internally tied to VDD via ~1 M\u03a9 (R_VMD) and to VSS via ~900 k\u03a9 (R_VMS)."+        "description": "Voltage sense terminal between VC1 and VMP, used as the overcurrent-3 (charger over-current / charger-detect) detection input. Internally tied to VDD via ~1 MΩ (R_VMD) and to VSS via ~900 kΩ (R_VMS)."       },       {         "number": "3",         "name": "DOP",         "type": "output",-        "description": "Discharge-control FET gate drive terminal (CMOS output, VSS\u2194VDD). Drives the external discharge-path N-MOSFET; goes low to disable discharge on overdischarge or overcurrent 1/2/3."+        "description": "Discharge-control FET gate drive terminal (CMOS output, VSS↔VDD). Drives the external discharge-path N-MOSFET; goes low to disable discharge on overdischarge or overcurrent 1/2/3."       },       {         "number": "4",@@ -56,13 +56,13 @@         "number": "5",         "name": "CDT",         "type": "passive",-        "description": "Delay-capacitor terminal for overdischarge detection delay (t_DL) and overcurrent-1 detection delay (t_IOV1). Typical external capacitor 0.1 \u00b5F sets t_DL \u2248 100 ms, t_IOV1 \u2248 10 ms."+        "description": "Delay-capacitor terminal for overdischarge detection delay (t_DL) and overcurrent-1 detection delay (t_IOV1). Typical external capacitor 0.1 µF sets t_DL ≈ 100 ms, t_IOV1 ≈ 10 ms."       },       {         "number": "6",         "name": "CCT",         "type": "passive",-        "description": "Delay-capacitor terminal for overcharge detection delay (t_CU). Typical external capacitor 0.1 \u00b5F sets t_CU \u2248 1 s."+        "description": "Delay-capacitor terminal for overcharge detection delay (t_CU). Typical external capacitor 0.1 µF sets t_CU ≈ 1 s."       },       {         "number": "7",@@ -86,13 +86,13 @@         "number": "10",         "name": "SEL",         "type": "input",-        "description": "3/4-series select input. Tie to VSS for 3-cell mode, tie to VDD for 4-cell mode. V_SELH \u2265 VDD\u00d70.8, V_SELL \u2264 VDD\u00d70.2."+        "description": "3/4-series select input. Tie to VSS for 3-cell mode, tie to VDD for 4-cell mode. V_SELH ≥ VDD×0.8, V_SELL ≤ VDD×0.2."       },       {         "number": "11",         "name": "CTL",         "type": "input",-        "description": "Control input to enable/disable the charge and discharge FETs (COP and DOP). V_CTLH \u2265 VDD\u00d70.8, V_CTLL \u2264 VDD\u00d70.2."+        "description": "Control input to enable/disable the charge and discharge FETs (COP and DOP). V_CTLH ≥ VDD×0.8, V_CTLL ≤ VDD×0.2."       },       {         "number": "12",@@ -186,5 +186,8 @@     "docs/slm8254aav-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file