component
SLB9670VQ20FW785XTMA1
Public Made by Adomby adom
Infineon Technologies Security Verification / Encryption ICs, QFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+270−8@@ -1,13 +1,280 @@ {+ "schema_version": 1,+ "type": "component", "slug": "slb9670vq20fw785xtma1",+ "title": "SLB9670VQ20FW785XTMA1",+ "brief": "Infineon Technologies Security Verification / Encryption ICs, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Infineon Technologies Security Verification / Encryption ICs, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "interface", "slb9670vq20fw785xtma1" ],+ "component": {+ "mpn": "SLB9670VQ20FW785XTMA1",+ "manufacturer": "Infineon Technologies",+ "package": "QFN-32-EP(5x5)",+ "pin_count": 32,+ "category": "Interface",+ "subcategory": "Security Verification / Encryption ICs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943111624409088",+ "parts": {+ "symbol": "slb9670vq20fw785xtma1.kicad_sym",+ "footprint": "slb9670vq20fw785xtma1.kicad_mod",+ "model_3d": "slb9670vq20fw785xtma1.glb",+ "model_3d_step": "slb9670vq20fw785xtma1.step",+ "lbr": "slb9670vq20fw785xtma1.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "NCI/VDD",+ "type": "passive",+ "description": "Not connected internally. Per TCG specification pin 1 is defined as VDD; VDD may be connected here for compliance."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin. All GND pins must be connected externally."+ },+ {+ "number": "3",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "4",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "5",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "6",+ "name": "GPIO",+ "type": "bidirectional",+ "description": "GPIO-Express-00 signal. Not used by the TPM2.0 device; may be left unconnected. Has internal pull-up resistor. Tri-State buffer (TS)."+ },+ {+ "number": "7",+ "name": "PP",+ "type": "input",+ "description": "Physical Presence input. Not used by the TPM2.0 device; may be left unconnected. Has internal pull-down resistor. Schmitt-Trigger input."+ },+ {+ "number": "8",+ "name": "VDD",+ "type": "power_in",+ "description": "Power Supply pin. Operating range 3.0-3.6 V (3.3 V typ) or 1.65-1.95 V (1.8 V typ). Must be bypassed to GND via 100 nF capacitors."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin. All GND pins must be connected externally."+ },+ {+ "number": "10",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "11",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "12",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "13",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "14",+ "name": "NCI/VDD",+ "type": "power_in",+ "description": "Not connected internally. Per TCG specification pin 14 is defined as VDD; VDD must be connected here for compliance and upwards compatibility to future TPMs."+ },+ {+ "number": "15",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "16",+ "name": "NCI/GND",+ "type": "passive",+ "description": "Not connected internally. Per TCG specification pin 16 is defined as GND; GND may be connected here for compliance."+ },+ {+ "number": "17",+ "name": "RST#",+ "type": "input",+ "description": "External Reset signal (active low). Asserting unconditionally resets the device; typically connected to the host PCIRST#. Weak internal pull-up. Schmitt-Trigger input."+ },+ {+ "number": "18",+ "name": "PIRQ#",+ "type": "output",+ "description": "Interrupt Request signal to the host (active low). Open-drain output; no internal pull-up resistor - external pull-up required."+ },+ {+ "number": "19",+ "name": "SCLK",+ "type": "input",+ "description": "SPI Clock input. Only SPI mode 0 is supported. Max clock 43 MHz at VDD=3.3 V. Schmitt-Trigger input."+ },+ {+ "number": "20",+ "name": "CS#",+ "type": "input",+ "description": "SPI Chip Select input (active low). Schmitt-Trigger input."+ },+ {+ "number": "21",+ "name": "MOSI",+ "type": "input",+ "description": "Master Out Slave In. SPI data received from the master. Schmitt-Trigger input."+ },+ {+ "number": "22",+ "name": "VDD",+ "type": "power_in",+ "description": "Power Supply pin. Operating range 3.0-3.6 V (3.3 V typ) or 1.65-1.95 V (1.8 V typ). Must be bypassed to GND via 100 nF capacitors."+ },+ {+ "number": "23",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin. All GND pins must be connected externally."+ },+ {+ "number": "24",+ "name": "MISO",+ "type": "output",+ "description": "Master In Slave Out. SPI data sent to the SPI bus master. Tri-State output."+ },+ {+ "number": "25",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "26",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "27",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "28",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "29",+ "name": "NC",+ "type": "unconnected",+ "description": "No Connect. Must be left floating (not connected externally)."+ },+ {+ "number": "30",+ "name": "NC",+ "type": "unconnected",+ "description": "No Connect. Must be left floating (not connected externally)."+ },+ {+ "number": "31",+ "name": "NCI",+ "type": "unconnected",+ "description": "Not connected internally. May be connected externally."+ },+ {+ "number": "32",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin. All GND pins must be connected externally. Also refer to exposed pad which is internally connected to GND."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943111624409088",+ "pages": 21,+ "sha256": "981b978c5b86d562",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 32,+ "described": 32,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Infineon Technologies",+ "Package": "QFN-32-EP(5x5)",+ "Category": "Interface",+ "Pins": "32"+ }+ },+ "variants": [+ {+ "mpn": "SLB9670VQ20FW785XTMA1SLB 9670VQ2.0",+ "kind": "packaging"+ },+ {+ "mpn": "SLB9670VQ20FW785XTMA1SLB 9670XQ2.0",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "slb9670vq20fw785xtma1"+ ],+ "discovery_pitch": "SLB9670VQ20FW785XTMA1 (Infineon Technologies) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +292,5 @@ "docs/slb9670vq20fw785xtma1-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }