SL2.1A

@@ -0,0 +1,58 @@+# SL2.1A++**CoreChips SL2 1A** · USB Converters · SOP-16++SL2.1A from CoreChips SL2 1A, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DM4 | bidirectional | Downstream Port 4 USB D- signal. Connects to the D- line of downstream USB device 4 with internal 15 kΩ pull-down (Rpd) and integrated 45 Ω high-speed termination. |+| 2 | DP4 | bidirectional | Downstream Port 4 USB D+ signal. Connects to the D+ line of downstream USB device 4 with internal 15 kΩ pull-down (Rpd) and integrated 45 Ω high-speed termination. |+| 3 | DM3 | bidirectional | Downstream Port 3 USB D- signal. Connects to the D- line of downstream USB device 3 with internal 15 kΩ pull-down and 45 Ω high-speed termination. |+| 4 | DP3 | bidirectional | Downstream Port 3 USB D+ signal. Connects to the D+ line of downstream USB device 3 with internal 15 kΩ pull-down and 45 Ω high-speed termination. |+| 5 | DM2 | bidirectional | Downstream Port 2 USB D- signal. Connects to the D- line of downstream USB device 2 with internal 15 kΩ pull-down and 45 Ω high-speed termination. |+| 6 | DP2 | bidirectional | Downstream Port 2 USB D+ signal. Connects to the D+ line of downstream USB device 2 with internal 15 kΩ pull-down and 45 Ω high-speed termination. |+| 7 | DM1 | bidirectional | Downstream Port 1 USB D- signal. Connects to the D- line of downstream USB device 1 with internal 15 kΩ pull-down and 45 Ω high-speed termination. |+| 8 | DP1 | bidirectional | Downstream Port 1 USB D+ signal. Connects to the D+ line of downstream USB device 1 with internal 15 kΩ pull-down and 45 Ω high-speed termination. |+| 9 | UDM | bidirectional | Upstream port USB D- signal. Connects to the host's D- line with internal 1.5 kΩ pull-up (Rpu) for high-speed device announcement and 45 Ω HS termination. |+| 10 | UDP | bidirectional | Upstream port USB D+ signal. Connects to the host's D+ line with internal 1.5 kΩ pull-up (Rpu) and 45 Ω HS termination. |+| 11 | VCC5 | power_in | 5 V main supply input. Feeds the internal 5V-to-3.3V LDO; single-supply operation for the whole chip. |+| 12 | VSS | power_in | Chip ground (0 V) reference for all analog and digital supplies. |+| 13 | VDD33 | power_out | 3.3 V LDO output derived from VCC5. Must be bypassed with a 4.7 µF capacitor to ground placed close to the pin; feeds the internal 3.3V-to-1.8V LDO through the PCB. |+| 14 | VDD18 | power_out | Digital 1.8 V LDO output. Must be bypassed with a 4.7 µF capacitor to ground placed close to the pin. |+| 15 | XOUT | output | 12 MHz crystal oscillator output pin. Connects to one terminal of a 12 MHz / CL=20 pF / 20 ppm crystal; no external load capacitors are required per datasheet. |+| 16 | XIN | input | 12 MHz crystal oscillator input pin. Connects to the other terminal of the 12 MHz / 20 pF / 20 ppm crystal; feeds the internal 12→480 MHz PLL. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | CoreChips SL2 1A |+| Package | SOP-16 |+| Category | Interface |+| Pins | 16 |++## Ordering variants++- `SL2.1A`+- `SL2.1ASL2.1S`+- `SL2.1ASL2.2S`+- `SL2.1ASL2.2Q`++## CAD (KiCad official)++- Symbol: `SL2.1A`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [CoreChips SL2 1A datasheet](docs/sl2-1a-datasheet.pdf) (21 pp, sha256 `9a55c6649643b949`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sl2-1a-datasheet.pdf)

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