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SIT1042AQT
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SIT CAN ICs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+55@@ -0,0 +1,55 @@+# SIT1042AQT++**SIT** · CAN ICs · SOP-8++SIT1042AQT from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TXD | input | Transmit data input from the CAN controller. Drives the differential bus: logic low = dominant, logic high = recessive. Internal pull-up to VIO (or VCC on non-VIO variants). TXD dominant timeout t_dom_TXD is typically 2 ms (0.8-4 ms), which forces the driver back to recessive if TXD is stuck low. |+| 2 | GND | power_in | Device ground reference for both the VCC supply and the CAN bus differential outputs. |+| 3 | VCC | power_in | Main 5V transceiver supply for the CAN bus driver stage. Operating range 4.5-5.5 V. Includes an integrated under-voltage lockout that forces the bus and RXD to the recessive state when VCC is below the UVLO threshold. |+| 4 | RXD | output | Receive data output to the CAN controller. Drives logic low when the bus is dominant and logic high when recessive. Push-pull output referenced to VIO (or VCC on non-VIO variants); I_OH ≈ −3 mA, I_OL ≈ 5 mA. |+| 5 | N.C. | unconnected | No internal connection on the SIT1042AQT / SIT1042AQT/1 / SIT1042AQTK / SIT1042AQTK/1 variants (no VIO level-shift supply on these ordering codes). May be left floating or tied to GND. On /3, /31, /K3, /K31 suffix variants this pin is instead the VIO I/O-level supply (1.8-5.5 V region, 2.8-5.5 V spec range) for 3.3 V MCU compatibility. |+| 6 | CANL | bidirectional | Low-side CAN bus I/O. In the dominant state driven to V_OL(D) ≈ 1.5 V (0.5-2.25 V) into a 60 Ω load; recessive state biased to ~0.5·VCC. Withstands ±58 V bus faults and supports −27 V to +32 V common-mode range on the receiver. |+| 7 | CANH | bidirectional | High-side CAN bus I/O. In the dominant state driven to V_OH(D) ≈ 3.5 V (2.75-4.5 V) into a 60 Ω load; recessive state biased to ~0.5·VCC. Withstands ±58 V bus faults and supports −27 V to +32 V common-mode range on the receiver. |+| 8 | STB | input | Mode-select input: low = high-speed normal mode, high = low-power standby mode with bus wake-up detection. Wake-up time t_WAKE typically 0.5-1.8 µs, standby-to-normal enable time t_EN ≤ 10 µs. Internal pull-up to VIO (or VCC) so the device defaults to standby if left floating. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | SIT |+| Package | SOP-8 |+| Category | Comm/UART |+| Pins | 8 |++## Ordering variants++- `SIT1042AQT`+- `SIT1042AQT/1`+- `SIT1042AQT/3`+- `SIT1042AQT/31`+- `SIT1042AQTK`+- `SIT1042AQTK/1`+- `SIT1042AQTK/3`+- `SIT1042AQTK/31`++## CAD (KiCad official)++- Symbol: `SIT1042AQT`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [SIT datasheet](docs/sit1042aqt-datasheet.pdf) (22 pp, sha256 `07c6ae984de4a519`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sit1042aqt-datasheet.pdf)
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