component
SI4914DY-T1-E3-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
si4914dy-t1-e3-vb: symbol repaired (body fitted to the names)
3 files changed
+34−25
si4914dy-t1-e3-vb.kicad_sym+9−9@@ -4,39 +4,39 @@ (property "Value" "SI4914DY-T1-E3-VB" (at 0 -10.16 0) (effects (font (size 1.27 1.27)))) (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) (symbol "SI4914DY-T1-E3-VB_0_1"- (rectangle (start -12.70 5.08) (end 12.70 -7.62)+ (rectangle (start -20.32 5.08) (end 20.32 -7.62) (stroke (width 0.254) (type default)) (fill (type background))) ) (symbol "SI4914DY-T1-E3-VB_1_1"- (pin passive line (at -17.78 2.54 0) (length 5.08)+ (pin passive line (at -25.40 2.54 0) (length 5.08) (name "DRAIN2" (effects (font (size 1.27 1.27)))) (number "1" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 0.00 0) (length 5.08)+ (pin passive line (at -25.40 0.00 0) (length 5.08) (name "DRAIN2" (effects (font (size 1.27 1.27)))) (number "2" (effects (font (size 1.27 1.27)))) )- (pin input line (at -17.78 -2.54 0) (length 5.08)+ (pin input line (at -25.40 -2.54 0) (length 5.08) (name "GATE1" (effects (font (size 1.27 1.27)))) (number "3" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 -5.08 0) (length 5.08)+ (pin passive line (at -25.40 -5.08 0) (length 5.08) (name "SOURCE1" (effects (font (size 1.27 1.27)))) (number "4" (effects (font (size 1.27 1.27)))) )- (pin input line (at 17.78 2.54 180) (length 5.08)+ (pin input line (at 25.40 2.54 180) (length 5.08) (name "GATE2" (effects (font (size 1.27 1.27)))) (number "8" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 0.00 180) (length 5.08)+ (pin passive line (at 25.40 0.00 180) (length 5.08) (name "DRAIN1/SOURCE2/CATHODE" (effects (font (size 1.27 1.27)))) (number "7" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 -2.54 180) (length 5.08)+ (pin passive line (at 25.40 -2.54 180) (length 5.08) (name "DRAIN1/SOURCE2/CATHODE" (effects (font (size 1.27 1.27)))) (number "6" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 -5.08 180) (length 5.08)+ (pin passive line (at 25.40 -5.08 180) (length 5.08) (name "DRAIN1/SOURCE2/CATHODE" (effects (font (size 1.27 1.27)))) (number "5" (effects (font (size 1.27 1.27)))) )
si4914dy-t1-e3-vb.lbr+24−15@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet</description> <packages> <package name="SOIC-8_3.9x4.9mm_P1.27mm"> <description>SOIC-8, 3.9 x 4.9 mm, 1.27 mm pitch</description>@@ -86,25 +86,26 @@ </packages> <symbols> <symbol name="SI4914DY-T1-E3-VB">- <wire x1="-12.7" y1="5.08" x2="12.7" y2="5.08" width="0.254" layer="94"/>- <wire x1="12.7" y1="5.08" x2="12.7" y2="-7.62" width="0.254" layer="94"/>- <wire x1="12.7" y1="-7.62" x2="-12.7" y2="-7.62" width="0.254" layer="94"/>- <wire x1="-12.7" y1="-7.62" x2="-12.7" y2="5.08" width="0.254" layer="94"/>+ <description>VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet</description>+ <wire x1="-20.32" y1="5.08" x2="20.32" y2="5.08" width="0.254" layer="94"/>+ <wire x1="20.32" y1="5.08" x2="20.32" y2="-7.62" width="0.254" layer="94"/>+ <wire x1="20.32" y1="-7.62" x2="-20.32" y2="-7.62" width="0.254" layer="94"/>+ <wire x1="-20.32" y1="-7.62" x2="-20.32" y2="5.08" width="0.254" layer="94"/> <text x="0.0000" y="7.6200" size="1.27" layer="95" align="center">>NAME</text> <text x="0.0000" y="-10.1600" size="1.27" layer="96" align="center">>VALUE</text>- <pin name="DRAIN2" x="-17.78" y="2.54" length="middle" direction="pas"/>- <pin name="DRAIN2@2" x="-17.78" y="0" length="middle" direction="pas"/>- <pin name="GATE1" x="-17.78" y="-2.54" length="middle" direction="in"/>- <pin name="SOURCE1" x="-17.78" y="-5.08" length="middle" direction="pas"/>- <pin name="GATE2" x="17.78" y="2.54" length="middle" direction="in" rot="R180"/>- <pin name="DRAIN1/SOURCE2/CATHODE" x="17.78" y="0" length="middle" direction="pas" rot="R180"/>- <pin name="DRAIN1/SOURCE2/CATHODE@2" x="17.78" y="-2.54" length="middle" direction="pas" rot="R180"/>- <pin name="DRAIN1/SOURCE2/CATHODE@3" x="17.78" y="-5.08" length="middle" direction="pas" rot="R180"/>+ <pin name="DRAIN2" x="-25.4" y="2.54" length="middle" direction="pas"/>+ <pin name="DRAIN2@2" x="-25.4" y="0" length="middle" direction="pas"/>+ <pin name="GATE1" x="-25.4" y="-2.54" length="middle" direction="in"/>+ <pin name="SOURCE1" x="-25.4" y="-5.08" length="middle" direction="pas"/>+ <pin name="GATE2" x="25.4" y="2.54" length="middle" direction="in" rot="R180"/>+ <pin name="DRAIN1/SOURCE2/CATHODE" x="25.4" y="0" length="middle" direction="pas" rot="R180"/>+ <pin name="DRAIN1/SOURCE2/CATHODE@2" x="25.4" y="-2.54" length="middle" direction="pas" rot="R180"/>+ <pin name="DRAIN1/SOURCE2/CATHODE@3" x="25.4" y="-5.08" length="middle" direction="pas" rot="R180"/> </symbol> </symbols> <devicesets> <deviceset name="SI4914DY-T1-E3-VB" prefix="U">- <description></description>+ <description>VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet</description> <gates> <gate name="G$1" symbol="SI4914DY-T1-E3-VB" x="0" y="0"/> </gates>@@ -120,7 +121,15 @@ <connect gate="G$1" pin="DRAIN1/SOURCE2/CATHODE@2" pad="6"/> <connect gate="G$1" pin="DRAIN1/SOURCE2/CATHODE@3" pad="5"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="SI4914DY-T1-E3-VB" constant="no"/>+ <attribute name="MANUFACTURER" value="VBsemi Elec" constant="no"/>+ <attribute name="DATASHEET" value="https://datasheet.lcsc.com/datasheet/pdf/190f7e4b7a824f2e447a39a55f66813c.pdf" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/si4914dy-t1-e3-vb" constant="no"/>+ <attribute name="LCSC_PN" value="C20417632" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
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