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Initial commit: component/si4228dy-t1-ge3

Ray ·2e7d5e5b12 ·28d ago
2 files changed +83
README.mdadded+49
@@ -0,0 +1,49 @@+# SI4228DY-T1-GE3++**Vishay Intertech** · MOSFETs · SO-8++SI4228DY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | S1 | passive | Source of MOSFET 1. Bonded together with pin 1 as the low-current source terminal of the first N-channel FET. |+| 2 | G1 | input | Gate of MOSFET 1. VGS rated ±12 V, VGS(th) 0.6 V to 1.4 V; drive to ≥4.5 V for full enhancement. |+| 3 | S2 | passive | Source of MOSFET 2. Source terminal of the second independent N-channel FET. |+| 4 | G2 | input | Gate of MOSFET 2. VGS rated ±12 V; drive to ≥4.5 V for full enhancement. |+| 5 | D2 | passive | Drain of MOSFET 2. Paralleled internally with pin 6 for current-carrying capability; VDS 25 V max. |+| 6 | D2 | passive | Drain of MOSFET 2 (paralleled with pin 5). Both drain pins of FET2 should be tied together on the PCB for full current rating and heat sinking. |+| 7 | D1 | passive | Drain of MOSFET 1 (paralleled with pin 8). VDS 25 V max. |+| 8 | D1 | passive | Drain of MOSFET 1 (paralleled with pin 7). Both drain pins of FET1 should be tied together on the PCB for full current rating and heat sinking. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Vishay Intertech |+| Package | SO-8 |+| Category | Transistors/Thyristors |+| Pins | 8 |++## Ordering variants++Same part, different packaging or reel option.++- `SI4228DY-T1-GE3`++## CAD (KiCad official)++- Symbol: `SI4228DY-T1-GE3`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SO-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923335900073985) (9 pp, sha256 `38d59c0301776d7d`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/si4228dy-t1-ge3-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "si4228dy-t1-ge3",+  "version": "0.1.0",+  "type": "component",+  "description": "Vishay Intertech MOSFETs, SO-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "transistors-thyristors",+    "si4228dy-t1-ge3"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "si4228dy-t1-ge3.kicad_sym",+    "si4228dy-t1-ge3.kicad_mod",+    "si4228dy-t1-ge3.glb",+    "si4228dy-t1-ge3.step",+    "si4228dy-t1-ge3.lbr",+    "docs/hero.png",+    "docs/si4228dy-t1-ge3-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file