component
SI4228DY-T1-GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+122−8@@ -1,13 +1,132 @@ {+ "schema_version": 1,+ "type": "component", "slug": "si4228dy-t1-ge3",+ "title": "SI4228DY-T1-GE3",+ "brief": "Vishay Intertech MOSFETs, SO-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Vishay Intertech MOSFETs, SO-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "transistors-thyristors", "si4228dy-t1-ge3" ],+ "component": {+ "mpn": "SI4228DY-T1-GE3",+ "manufacturer": "Vishay Intertech",+ "package": "SO-8",+ "pin_count": 8,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923335900073985",+ "parts": {+ "symbol": "si4228dy-t1-ge3.kicad_sym",+ "footprint": "si4228dy-t1-ge3.kicad_mod",+ "model_3d": "si4228dy-t1-ge3.glb",+ "model_3d_step": "si4228dy-t1-ge3.step",+ "lbr": "si4228dy-t1-ge3.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "S1",+ "type": "passive",+ "description": "Source of MOSFET 1. Bonded together with pin 1 as the low-current source terminal of the first N-channel FET."+ },+ {+ "number": "2",+ "name": "G1",+ "type": "input",+ "description": "Gate of MOSFET 1. VGS rated \u00b112 V, VGS(th) 0.6 V to 1.4 V; drive to \u22654.5 V for full enhancement."+ },+ {+ "number": "3",+ "name": "S2",+ "type": "passive",+ "description": "Source of MOSFET 2. Source terminal of the second independent N-channel FET."+ },+ {+ "number": "4",+ "name": "G2",+ "type": "input",+ "description": "Gate of MOSFET 2. VGS rated \u00b112 V; drive to \u22654.5 V for full enhancement."+ },+ {+ "number": "5",+ "name": "D2",+ "type": "passive",+ "description": "Drain of MOSFET 2. Paralleled internally with pin 6 for current-carrying capability; VDS 25 V max."+ },+ {+ "number": "6",+ "name": "D2",+ "type": "passive",+ "description": "Drain of MOSFET 2 (paralleled with pin 5). Both drain pins of FET2 should be tied together on the PCB for full current rating and heat sinking."+ },+ {+ "number": "7",+ "name": "D1",+ "type": "passive",+ "description": "Drain of MOSFET 1 (paralleled with pin 8). VDS 25 V max."+ },+ {+ "number": "8",+ "name": "D1",+ "type": "passive",+ "description": "Drain of MOSFET 1 (paralleled with pin 7). Both drain pins of FET1 should be tied together on the PCB for full current rating and heat sinking."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923335900073985",+ "pages": 9,+ "sha256": "38d59c0301776d7d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Vishay Intertech",+ "Package": "SO-8",+ "Category": "Transistors/Thyristors",+ "Pins": "8"+ }+ },+ "variants": [+ {+ "mpn": "SI4228DY-T1-GE3",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "si4228dy-t1-ge3"+ ],+ "discovery_pitch": "SI4228DY-T1-GE3 (Vishay Intertech) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +144,5 @@ "docs/si4228dy-t1-ge3-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }