component
SGM836-ADJXN6G
Public Made by Adomby adom
SGMICRO Supervisor and Reset ICs, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+9−6@@ -32,7 +32,7 @@ "number": "1", "name": "nRESET", "type": "output",- "description": "Active-low, open-drain reset output. Held low while SENSE < VIT or nMR is logic low, and remains low for the reset timeout period tD after both conditions are cleared. Requires an external 10k\u03a9 to 1M\u03a9 pull-up (to a rail up to 6.5V, may exceed VDD). Sink capability IOL = 0.4mA at VDD \u2265 1.3V and 1mA at VDD \u2265 1.8V; leakage 1\u00b5A max when de-asserted."+ "description": "Active-low, open-drain reset output. Held low while SENSE < VIT or nMR is logic low, and remains low for the reset timeout period tD after both conditions are cleared. Requires an external 10kΩ to 1MΩ pull-up (to a rail up to 6.5V, may exceed VDD). Sink capability IOL = 0.4mA at VDD ≥ 1.3V and 1mA at VDD ≥ 1.8V; leakage 1µA max when de-asserted." }, { "number": "2",@@ -44,25 +44,25 @@ "number": "3", "name": "nMR", "type": "input",- "description": "Active-low manual reset input. Pulling nMR low asserts nRESET. Internally pulled up to VDD by a ~100k\u03a9 resistor (50k\u03a9 min). Logic thresholds VIL \u2264 0.3\u00d7VDD, VIH \u2265 0.7\u00d7VDD; propagation delay to nRESET is 250ns typ and requires a min pulse width tnMR \u2265 100ns."+ "description": "Active-low manual reset input. Pulling nMR low asserts nRESET. Internally pulled up to VDD by a ~100kΩ resistor (50kΩ min). Logic thresholds VIL ≤ 0.3×VDD, VIH ≥ 0.7×VDD; propagation delay to nRESET is 250ns typ and requires a min pulse width tnMR ≥ 100ns." }, { "number": "4", "name": "CT", "type": "input",- "description": "Reset timeout delay programming pin. Leave open for the fixed ~20ms delay; connect a 40k\u03a9 to 200k\u03a9 resistor from CT to VDD for a ~300ms fixed delay; or connect a capacitor \u2265 100pF from CT to GND for a programmable 1.25ms to 10s delay. Internal CT source ramps to VTH-RAMP \u2248 1.206V; absolute max range \u22120.3V to VDD + 0.3V."+ "description": "Reset timeout delay programming pin. Leave open for the fixed ~20ms delay; connect a 40kΩ to 200kΩ resistor from CT to VDD for a ~300ms fixed delay; or connect a capacitor ≥ 100pF from CT to GND for a programmable 1.25ms to 10s delay. Internal CT source ramps to VTH-RAMP ≈ 1.206V; absolute max range −0.3V to VDD + 0.3V." }, { "number": "5", "name": "SENSE", "type": "input",- "description": "Dedicated voltage monitor input. nRESET is asserted when VSENSE falls below the negative-going threshold VIT (0.405V nominal for the ADJ variant; factory-set to 0.9V-5V on fixed versions). On the ADJ version input current is \u00b125nA max; VSENSE range 0V to 6.5V; SENSE-to-nRESET delay tRP0 \u2248 100\u00b5s."+ "description": "Dedicated voltage monitor input. nRESET is asserted when VSENSE falls below the negative-going threshold VIT (0.405V nominal for the ADJ variant; factory-set to 0.9V-5V on fixed versions). On the ADJ version input current is ±25nA max; VSENSE range 0V to 6.5V; SENSE-to-nRESET delay tRP0 ≈ 100µs." }, { "number": "6", "name": "VDD", "type": "power_in",- "description": "Supply voltage input, operating range 1.65V to 6.5V (absolute max 7V). Quiescent current IDD \u2248 0.6\u00b5A typ at VDD = 3.3V and 0.9\u00b5A typ at VDD = 6.5V with nRESET not asserted and CT open."+ "description": "Supply voltage input, operating range 1.65V to 6.5V (absolute max 7V). Quiescent current IDD ≈ 0.6µA typ at VDD = 3.3V and 0.9µA typ at VDD = 6.5V with nRESET not asserted and CT open." } ], "provenance": {@@ -140,5 +140,8 @@ "docs/sgm836-adjxn6g-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }