component
SCT2630ASTER
Public Made by Adomby adom
SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+49@@ -0,0 +1,49 @@+# SCT2630ASTER++**SCT** · DC-DC Converters · ESOP-8++SCT2630ASTER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | BOOT | power_in | Power supply bias for high-side power MOSFET gate driver. Connect a 0.1µF bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V. |+| 2 | VIN | power_in | Input supply voltage, 4.5V to 60V operating range (absolute max 65V). Connect a local high-frequency bypass capacitor from VIN to GND as close as possible to the pin. |+| 3 | EN | input | Enable input with internal 1µA pull-up current source (3.6µA once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V. |+| 4 | RT/CLK | bidirectional | Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(kΩ) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high ≥2V, low ≤0.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency. |+| 5 | FB | input | Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V ±1% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling). |+| 6 | COMP | output | Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm ≈ 300µS, ±30µA source/sink. |+| 7 | GND | power_in | Ground return for the device. Electrically connected to the exposed thermal pad. |+| 8 | SW | output | Regulator switching output - source of the integrated 80mΩ high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return. |+| 9 | Thermal Pad | passive | Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (θJA ≈ 42°C/W). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | SCT |+| Package | ESOP-8 |+| Category | PMIC |+| Pins | 9 |++## Ordering variants++- `SCT2630ASTERSCT2630ASTE`+- `SCT2630ASTER`++## CAD (KiCad official)++- Symbol: `SCT2630ASTER`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`+- 3D model: ESOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [SCT datasheet](docs/sct2630aster-datasheet.pdf) (23 pp, sha256 `616843ced2651fa2`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sct2630aster-datasheet.pdf)
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