SCT2630ASTER

@@ -26,13 +26,15 @@       "model_3d_step": "sct2630aster.step",       "lbr": "sct2630aster.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C2693818"+    },     "pins": [       {         "number": "1",         "name": "BOOT",         "type": "power_in",-        "description": "Power supply bias for high-side power MOSFET gate driver. Connect a 0.1µF bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V."+        "description": "Power supply bias for high-side power MOSFET gate driver. Connect a 0.1\u00b5F bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V."       },       {         "number": "2",@@ -44,25 +46,25 @@         "number": "3",         "name": "EN",         "type": "input",-        "description": "Enable input with internal 1µA pull-up current source (3.6µA once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V."+        "description": "Enable input with internal 1\u00b5A pull-up current source (3.6\u00b5A once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V."       },       {         "number": "4",         "name": "RT/CLK",         "type": "bidirectional",-        "description": "Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(kΩ) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high ≥2V, low ≤0.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency."+        "description": "Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(k\u03a9) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high \u22652V, low \u22640.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency."       },       {         "number": "5",         "name": "FB",         "type": "input",-        "description": "Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V ±1% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling)."+        "description": "Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V \u00b11% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling)."       },       {         "number": "6",         "name": "COMP",         "type": "output",-        "description": "Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm ≈ 300µS, ±30µA source/sink."+        "description": "Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm \u2248 300\u00b5S, \u00b130\u00b5A source/sink."       },       {         "number": "7",@@ -74,13 +76,13 @@         "number": "8",         "name": "SW",         "type": "output",-        "description": "Regulator switching output - source of the integrated 80mΩ high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return."+        "description": "Regulator switching output - source of the integrated 80m\u03a9 high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return."       },       {         "number": "9",         "name": "Thermal Pad",         "type": "passive",-        "description": "Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (θJA ≈ 42°C/W)."+        "description": "Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (\u03b8JA \u2248 42\u00b0C/W)."       }     ],     "provenance": {

@@ -63,6 +63,18 @@   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="9" x="0.0000" y="-0.0000" dx="2.4100" dy="3.3000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -71,7 +83,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="SCT2630ASTER">@@ -86,7 +98,7 @@   <pin name="EN" x="-17.78" y="0" length="middle" direction="in"/>   <pin name="RT/CLK" x="-17.78" y="-2.54" length="middle" direction="io"/>   <pin name="FB" x="-17.78" y="-5.08" length="middle" direction="in"/>-  <pin name="Thermal Pad" x="17.78" y="2.54" length="middle" direction="pas" rot="R180"/>+  <pin name="Thermal_Pad" x="17.78" y="2.54" length="middle" direction="pas" rot="R180"/>   <pin name="SW" x="17.78" y="0" length="middle" direction="out" rot="R180"/>   <pin name="GND" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>   <pin name="COMP" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/>@@ -106,12 +118,18 @@         <connect gate="G$1" pin="EN" pad="3"/>         <connect gate="G$1" pin="RT/CLK" pad="4"/>         <connect gate="G$1" pin="FB" pad="5"/>-        <connect gate="G$1" pin="Thermal Pad" pad="9"/>+        <connect gate="G$1" pin="Thermal_Pad" pad="9"/>         <connect gate="G$1" pin="SW" pad="8"/>         <connect gate="G$1" pin="GND" pad="7"/>         <connect gate="G$1" pin="COMP" pad="6"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="SCT2630ASTER" constant="no"/>+          <attribute name="MANUFACTURER" value="SCT" constant="no"/>+          <attribute name="LCSC_PN" value="C2693818" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>