← Commit history

sct2630aster: factory component page (tier=lcsc)

Ray ·659f505f41 · ·parent 3407f0a
1 file changed +122−8
page.json+122−8
@@ -1,13 +1,132 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sct2630aster",+  "title": "SCT2630ASTER",+  "brief": "SCT DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "SCT DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "pmic",     "sct2630aster"   ],+  "component": {+    "mpn": "SCT2630ASTER",+    "manufacturer": "SCT",+    "package": "ESOP-8",+    "pin_count": 9,+    "category": "PMIC",+    "subcategory": "DC-DC Converters",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/56d1acd1ca98d7258b963bc23c796dfb.pdf",+    "parts": {+      "symbol": "sct2630aster.kicad_sym",+      "footprint": "sct2630aster.kicad_mod",+      "model_3d": "sct2630aster.glb",+      "model_3d_step": "sct2630aster.step",+      "lbr": "sct2630aster.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "BOOT",+        "type": "power_in",+        "description": "Power supply bias for high-side power MOSFET gate driver. Connect a 0.1\u00b5F bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V."+      },+      {+        "number": "2",+        "name": "VIN",+        "type": "power_in",+        "description": "Input supply voltage, 4.5V to 60V operating range (absolute max 65V). Connect a local high-frequency bypass capacitor from VIN to GND as close as possible to the pin."+      },+      {+        "number": "3",+        "name": "EN",+        "type": "input",+        "description": "Enable input with internal 1\u00b5A pull-up current source (3.6\u00b5A once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V."+      },+      {+        "number": "4",+        "name": "RT/CLK",+        "type": "bidirectional",+        "description": "Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(k\u03a9) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high \u22652V, low \u22640.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency."+      },+      {+        "number": "5",+        "name": "FB",+        "type": "input",+        "description": "Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V \u00b11% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling)."+      },+      {+        "number": "6",+        "name": "COMP",+        "type": "output",+        "description": "Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm \u2248 300\u00b5S, \u00b130\u00b5A source/sink."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return for the device. Electrically connected to the exposed thermal pad."+      },+      {+        "number": "8",+        "name": "SW",+        "type": "output",+        "description": "Regulator switching output - source of the integrated 80m\u03a9 high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return."+      },+      {+        "number": "9",+        "name": "Thermal Pad",+        "type": "passive",+        "description": "Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (\u03b8JA \u2248 42\u00b0C/W)."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/56d1acd1ca98d7258b963bc23c796dfb.pdf",+        "pages": 23,+        "sha256": "616843ced2651fa2",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 9,+        "described": 9,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "SCT",+      "Package": "ESOP-8",+      "Category": "PMIC",+      "Pins": "9"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "sct2630aster"+  ],+  "discovery_pitch": "SCT2630ASTER (SCT) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +144,5 @@     "docs/sct2630aster-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file