component
SCT2630ASTER
Public Made by Adomby adom
SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+11−8@@ -32,7 +32,7 @@ "number": "1", "name": "BOOT", "type": "power_in",- "description": "Power supply bias for high-side power MOSFET gate driver. Connect a 0.1\u00b5F bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V."+ "description": "Power supply bias for high-side power MOSFET gate driver. Connect a 0.1µF bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V." }, { "number": "2",@@ -44,25 +44,25 @@ "number": "3", "name": "EN", "type": "input",- "description": "Enable input with internal 1\u00b5A pull-up current source (3.6\u00b5A once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V."+ "description": "Enable input with internal 1µA pull-up current source (3.6µA once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V." }, { "number": "4", "name": "RT/CLK", "type": "bidirectional",- "description": "Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(k\u03a9) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high \u22652V, low \u22640.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency."+ "description": "Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(kΩ) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high ≥2V, low ≤0.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency." }, { "number": "5", "name": "FB", "type": "input",- "description": "Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V \u00b11% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling)."+ "description": "Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V ±1% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling)." }, { "number": "6", "name": "COMP", "type": "output",- "description": "Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm \u2248 300\u00b5S, \u00b130\u00b5A source/sink."+ "description": "Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm ≈ 300µS, ±30µA source/sink." }, { "number": "7",@@ -74,13 +74,13 @@ "number": "8", "name": "SW", "type": "output",- "description": "Regulator switching output - source of the integrated 80m\u03a9 high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return."+ "description": "Regulator switching output - source of the integrated 80mΩ high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return." }, { "number": "9", "name": "Thermal Pad", "type": "passive",- "description": "Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (\u03b8JA \u2248 42\u00b0C/W)."+ "description": "Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (θJA ≈ 42°C/W)." } ], "provenance": {@@ -144,5 +144,8 @@ "docs/sct2630aster-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }