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Set visibility: public

Ray ·53467d5c0b · ·parent 1fa31c0
1 file changed +8−5
page.json+8−5
@@ -32,7 +32,7 @@         "number": "1",         "name": "FLG",         "type": "output",-        "description": "Open-drain fault flag output. Asserts low (typ. 20 \u03a9 pull-down, IFLG_OFF \u2264 1 \u03bcA leakage when off) after a 12 ms (typ.) delay when an over-current, thermal-shutdown, or reverse-current fault is detected. Requires an external 10 k\u03a9-100 k\u03a9 pull-up resistor to the USB controller supply. Absolute-max flag voltage 6.5 V."+        "description": "Open-drain fault flag output. Asserts low (typ. 20 Ω pull-down, IFLG_OFF ≤ 1 μA leakage when off) after a 12 ms (typ.) delay when an over-current, thermal-shutdown, or reverse-current fault is detected. Requires an external 10 kΩ-100 kΩ pull-up resistor to the USB controller supply. Absolute-max flag voltage 6.5 V."       },       {         "number": "2",@@ -44,19 +44,19 @@         "number": "3",         "name": "EN",         "type": "input",-        "description": "Chip enable input (active-high on the RT9711A variant). Logic-high (VIH \u2265 2.0 V) turns the internal N-MOSFET switch on; logic-low (VIL \u2264 0.8 V) turns it off. Input range 0 V to 5.5 V, input leakage 0.01 \u03bcA typ. Must never be left floating. When disabled the pin is pulled low internally through ~75 \u03a9 (RDS shutdown)."+        "description": "Chip enable input (active-high on the RT9711A variant). Logic-high (VIH ≥ 2.0 V) turns the internal N-MOSFET switch on; logic-low (VIL ≤ 0.8 V) turns it off. Input range 0 V to 5.5 V, input leakage 0.01 μA typ. Must never be left floating. When disabled the pin is pulled low internally through ~75 Ω (RDS shutdown)."       },       {         "number": "4",         "name": "VIN",         "type": "power_in",-        "description": "Power input to the internal high-side N-MOSFET switch and to the internal bias/charge-pump/UVLO circuitry. Recommended operating range 2.5 V to 5.5 V (absolute max 6.5 V). Decouple locally with a 1 \u03bcF CIN capacitor to GND. UVLO releases at ~1.7 V rising."+        "description": "Power input to the internal high-side N-MOSFET switch and to the internal bias/charge-pump/UVLO circuitry. Recommended operating range 2.5 V to 5.5 V (absolute max 6.5 V). Decouple locally with a 1 μF CIN capacitor to GND. UVLO releases at ~1.7 V rising."       },       {         "number": "5",         "name": "VOUT",         "type": "power_out",-        "description": "Switched power output (drain of the internal N-MOSFET) to the downstream USB port/load. Delivers up to 1.5 A continuous (current limit ILIM = 2.5 A typ., 1.6-3.2 A). RDS(on) 80 m\u03a9 typ. at VIN = 5 V, IOUT = 1 A. A low-ESR \u2265150 \u03bcF aluminum/tantalum bulk capacitor plus a 10 \u03bcF ceramic to GND is recommended to meet the USB VBUS 330 mV droop requirement. Can be forced higher than VIN when off (no body diode)."+        "description": "Switched power output (drain of the internal N-MOSFET) to the downstream USB port/load. Delivers up to 1.5 A continuous (current limit ILIM = 2.5 A typ., 1.6-3.2 A). RDS(on) 80 mΩ typ. at VIN = 5 V, IOUT = 1 A. A low-ESR ≥150 μF aluminum/tantalum bulk capacitor plus a 10 μF ceramic to GND is recommended to meet the USB VBUS 330 mV droop requirement. Can be forced higher than VIN when off (no body diode)."       }     ],     "provenance": {@@ -120,5 +120,8 @@     "docs/rt9711agb-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file