component
RT9711AGB
Public Made by Adomby adom
Richtek Tech AC-DC Controllers and Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C250543). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+27−7
page.json+7−5@@ -26,13 +26,15 @@ "model_3d_step": "rt9711agb.step", "lbr": "rt9711agb.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C250543"+ }, "pins": [ { "number": "1", "name": "FLG", "type": "output",- "description": "Open-drain fault flag output. Asserts low (typ. 20 Ω pull-down, IFLG_OFF ≤ 1 μA leakage when off) after a 12 ms (typ.) delay when an over-current, thermal-shutdown, or reverse-current fault is detected. Requires an external 10 kΩ-100 kΩ pull-up resistor to the USB controller supply. Absolute-max flag voltage 6.5 V."+ "description": "Open-drain fault flag output. Asserts low (typ. 20 \u03a9 pull-down, IFLG_OFF \u2264 1 \u03bcA leakage when off) after a 12 ms (typ.) delay when an over-current, thermal-shutdown, or reverse-current fault is detected. Requires an external 10 k\u03a9-100 k\u03a9 pull-up resistor to the USB controller supply. Absolute-max flag voltage 6.5 V." }, { "number": "2",@@ -44,19 +46,19 @@ "number": "3", "name": "EN", "type": "input",- "description": "Chip enable input (active-high on the RT9711A variant). Logic-high (VIH ≥ 2.0 V) turns the internal N-MOSFET switch on; logic-low (VIL ≤ 0.8 V) turns it off. Input range 0 V to 5.5 V, input leakage 0.01 μA typ. Must never be left floating. When disabled the pin is pulled low internally through ~75 Ω (RDS shutdown)."+ "description": "Chip enable input (active-high on the RT9711A variant). Logic-high (VIH \u2265 2.0 V) turns the internal N-MOSFET switch on; logic-low (VIL \u2264 0.8 V) turns it off. Input range 0 V to 5.5 V, input leakage 0.01 \u03bcA typ. Must never be left floating. When disabled the pin is pulled low internally through ~75 \u03a9 (RDS shutdown)." }, { "number": "4", "name": "VIN", "type": "power_in",- "description": "Power input to the internal high-side N-MOSFET switch and to the internal bias/charge-pump/UVLO circuitry. Recommended operating range 2.5 V to 5.5 V (absolute max 6.5 V). Decouple locally with a 1 μF CIN capacitor to GND. UVLO releases at ~1.7 V rising."+ "description": "Power input to the internal high-side N-MOSFET switch and to the internal bias/charge-pump/UVLO circuitry. Recommended operating range 2.5 V to 5.5 V (absolute max 6.5 V). Decouple locally with a 1 \u03bcF CIN capacitor to GND. UVLO releases at ~1.7 V rising." }, { "number": "5", "name": "VOUT", "type": "power_out",- "description": "Switched power output (drain of the internal N-MOSFET) to the downstream USB port/load. Delivers up to 1.5 A continuous (current limit ILIM = 2.5 A typ., 1.6-3.2 A). RDS(on) 80 mΩ typ. at VIN = 5 V, IOUT = 1 A. A low-ESR ≥150 μF aluminum/tantalum bulk capacitor plus a 10 μF ceramic to GND is recommended to meet the USB VBUS 330 mV droop requirement. Can be forced higher than VIN when off (no body diode)."+ "description": "Switched power output (drain of the internal N-MOSFET) to the downstream USB port/load. Delivers up to 1.5 A continuous (current limit ILIM = 2.5 A typ., 1.6-3.2 A). RDS(on) 80 m\u03a9 typ. at VIN = 5 V, IOUT = 1 A. A low-ESR \u2265150 \u03bcF aluminum/tantalum bulk capacitor plus a 10 \u03bcF ceramic to GND is recommended to meet the USB VBUS 330 mV droop requirement. Can be forced higher than VIN when off (no body diode)." } ], "provenance": {
rt9711agb.lbr+20−2@@ -59,6 +59,18 @@ <smd name="3" x="-1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="5" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.4500" y="1.5100"/>+ <vertex x="-1.6900" y="1.8400"/>+ <vertex x="-1.2100" y="1.8400"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.4000" y="1.4500"/>+ <vertex x="0.8000" y="1.4500"/>+ <vertex x="0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="1.0500"/>+ </polygon> <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/> <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="RT9711AGB">@@ -100,7 +112,13 @@ <connect gate="G$1" pin="VOUT" pad="5"/> <connect gate="G$1" pin="VIN" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="RT9711AGB" constant="no"/>+ <attribute name="MANUFACTURER" value="Richtek Tech" constant="no"/>+ <attribute name="LCSC_PN" value="C250543" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>