RT8296AHZSP

@@ -0,0 +1,51 @@+# RT8296AHZSP++**Richtek Tech** · DC-DC Converters · SOP-8-EP++RT8296AHZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | BOOT | passive | Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW to provide the boosted gate-drive voltage for the internal high-side N-MOSFET. Absolute max 31.3V; VBOOT − VSW max 6V. |+| 2 | VIN | power_in | Input supply voltage, 4.5V to 23V operating range (absolute max 25V). Must be bypassed with a suitably large ceramic capacitor (e.g. 10μF x 2) placed close to the pin. |+| 3 | SW | power_out | Switch (phase) node. Connect to the external L-C output filter. This is the drain node of the internal high-side and source of the internal low-side N-MOSFETs (RDS(ON) ≈ 85mΩ each), swinging between GND and VIN at 340kHz. |+| 4 | GND | power_in | Ground return. Pin 4 and the exposed pad (pin 9) must both be tied to ground; solder the exposed pad to a large PCB copper area for maximum power dissipation (θJA = 75°C/W, θJC = 15°C/W). |+| 5 | FB | input | Feedback input. Regulates to an internal 0.8V (±1.5%) reference. For adjustable output, connect an external resistive divider from VOUT to FB to GND to set the output voltage from 0.8V to 20V. |+| 6 | COMP | output | Error-amplifier compensation node (GEA ≈ 940μA/V). Connect a series RC network from COMP to GND to compensate the current-mode control loop; an optional capacitor from COMP to GND may be added for a high-frequency pole. |+| 7 | EN | input | Enable input. Logic-high (VIH ≥ 2.7V) enables the converter; logic-low (VIL ≤ 0.4V) forces shutdown, reducing supply current to <3μA. Tie to VIN through a 100kΩ pull-up for automatic startup. Absolute max 6V. |+| 8 | SS | passive | Soft-start control input. Connect a capacitor from SS to GND to program the soft-start ramp period; ISS ≈ 6μA charging current. A 0.1μF capacitor sets tSS ≈ 13.5ms. |+| 9 | GND (Exposed Pad) | power_in | Exposed thermal pad on the bottom of the SOP-8 package. Must be soldered to a large PCB ground plane and electrically connected to GND for proper operation and maximum power dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Richtek Tech |+| Package | SOP-8-EP |+| Category | PMIC |+| Pins | 9 |++## Ordering variants++- `RT8296AHZSPHZSP`+- `RT8296AHZSPLZSP`+- `RT8296AHZSPHGSP`+- `RT8296AHZSPLGSP`++## CAD (KiCad official)++- Symbol: `RT8296AHZSP`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8-EP (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Richtek Tech datasheet](docs/rt8296ahzsp-datasheet.pdf) (14 pp, sha256 `65b4ec20534cc22d`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/rt8296ahzsp-datasheet.pdf)

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