← Commit history

orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C259730). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.

Ray ·7e1d30d03e · ·parent d431d05
2 files changed +33−13
page.json+11−9
@@ -26,55 +26,57 @@       "model_3d_step": "rt8296ahzsp.step",       "lbr": "rt8296ahzsp.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C259730"+    },     "pins": [       {         "number": "1",         "name": "BOOT",         "type": "passive",-        "description": "Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW to provide the boosted gate-drive voltage for the internal high-side N-MOSFET. Absolute max 31.3V; VBOOT − VSW max 6V."+        "description": "Bootstrap for high-side gate driver. Connect a 0.1\u03bcF or greater ceramic capacitor from BOOT to SW to provide the boosted gate-drive voltage for the internal high-side N-MOSFET. Absolute max 31.3V; VBOOT \u2212 VSW max 6V."       },       {         "number": "2",         "name": "VIN",         "type": "power_in",-        "description": "Input supply voltage, 4.5V to 23V operating range (absolute max 25V). Must be bypassed with a suitably large ceramic capacitor (e.g. 10μF x 2) placed close to the pin."+        "description": "Input supply voltage, 4.5V to 23V operating range (absolute max 25V). Must be bypassed with a suitably large ceramic capacitor (e.g. 10\u03bcF x 2) placed close to the pin."       },       {         "number": "3",         "name": "SW",         "type": "power_out",-        "description": "Switch (phase) node. Connect to the external L-C output filter. This is the drain node of the internal high-side and source of the internal low-side N-MOSFETs (RDS(ON) ≈ 85mΩ each), swinging between GND and VIN at 340kHz."+        "description": "Switch (phase) node. Connect to the external L-C output filter. This is the drain node of the internal high-side and source of the internal low-side N-MOSFETs (RDS(ON) \u2248 85m\u03a9 each), swinging between GND and VIN at 340kHz."       },       {         "number": "4",         "name": "GND",         "type": "power_in",-        "description": "Ground return. Pin 4 and the exposed pad (pin 9) must both be tied to ground; solder the exposed pad to a large PCB copper area for maximum power dissipation (θJA = 75°C/W, θJC = 15°C/W)."+        "description": "Ground return. Pin 4 and the exposed pad (pin 9) must both be tied to ground; solder the exposed pad to a large PCB copper area for maximum power dissipation (\u03b8JA = 75\u00b0C/W, \u03b8JC = 15\u00b0C/W)."       },       {         "number": "5",         "name": "FB",         "type": "input",-        "description": "Feedback input. Regulates to an internal 0.8V (±1.5%) reference. For adjustable output, connect an external resistive divider from VOUT to FB to GND to set the output voltage from 0.8V to 20V."+        "description": "Feedback input. Regulates to an internal 0.8V (\u00b11.5%) reference. For adjustable output, connect an external resistive divider from VOUT to FB to GND to set the output voltage from 0.8V to 20V."       },       {         "number": "6",         "name": "COMP",         "type": "output",-        "description": "Error-amplifier compensation node (GEA ≈ 940μA/V). Connect a series RC network from COMP to GND to compensate the current-mode control loop; an optional capacitor from COMP to GND may be added for a high-frequency pole."+        "description": "Error-amplifier compensation node (GEA \u2248 940\u03bcA/V). Connect a series RC network from COMP to GND to compensate the current-mode control loop; an optional capacitor from COMP to GND may be added for a high-frequency pole."       },       {         "number": "7",         "name": "EN",         "type": "input",-        "description": "Enable input. Logic-high (VIH ≥ 2.7V) enables the converter; logic-low (VIL ≤ 0.4V) forces shutdown, reducing supply current to <3μA. Tie to VIN through a 100kΩ pull-up for automatic startup. Absolute max 6V."+        "description": "Enable input. Logic-high (VIH \u2265 2.7V) enables the converter; logic-low (VIL \u2264 0.4V) forces shutdown, reducing supply current to <3\u03bcA. Tie to VIN through a 100k\u03a9 pull-up for automatic startup. Absolute max 6V."       },       {         "number": "8",         "name": "SS",         "type": "passive",-        "description": "Soft-start control input. Connect a capacitor from SS to GND to program the soft-start ramp period; ISS ≈ 6μA charging current. A 0.1μF capacitor sets tSS ≈ 13.5ms."+        "description": "Soft-start control input. Connect a capacitor from SS to GND to program the soft-start ramp period; ISS \u2248 6\u03bcA charging current. A 0.1\u03bcF capacitor sets tSS \u2248 13.5ms."       },       {         "number": "9",
rt8296ahzsp.lbr+22−4
@@ -63,6 +63,18 @@   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="9" x="0.0000" y="-0.0000" dx="2.2900" dy="3.0000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -71,7 +83,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="RT8296AHZSP">@@ -86,7 +98,7 @@   <pin name="SW" x="-17.78" y="0" length="middle" direction="out"/>   <pin name="GND" x="-17.78" y="-2.54" length="middle" direction="pwr"/>   <pin name="FB" x="-17.78" y="-5.08" length="middle" direction="in"/>-  <pin name="GND (Exposed Pad)" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+  <pin name="GND_Exposed_Pad" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>   <pin name="SS" x="17.78" y="0" length="middle" direction="pas" rot="R180"/>   <pin name="EN" x="17.78" y="-2.54" length="middle" direction="in" rot="R180"/>   <pin name="COMP" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/>@@ -106,12 +118,18 @@         <connect gate="G$1" pin="SW" pad="3"/>         <connect gate="G$1" pin="GND" pad="4"/>         <connect gate="G$1" pin="FB" pad="5"/>-        <connect gate="G$1" pin="GND (Exposed Pad)" pad="9"/>+        <connect gate="G$1" pin="GND_Exposed_Pad" pad="9"/>         <connect gate="G$1" pin="SS" pad="8"/>         <connect gate="G$1" pin="EN" pad="7"/>         <connect gate="G$1" pin="COMP" pad="6"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="RT8296AHZSP" constant="no"/>+          <attribute name="MANUFACTURER" value="Richtek Tech" constant="no"/>+          <attribute name="LCSC_PN" value="C259730" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>