component
RT7272BGSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (ep_dropped, 8 pins; datasheet EP 2.4x3.4mm, land 2.41x3.3mm (Δ0.11mm))
3 files changed
+15−15
README.md+1−1@@ -34,7 +34,7 @@ RT7272BGSP from Richtek Tech, in a SOIC-8-EP. Pinout and pin descriptions extrac ## CAD (KiCad official) - Symbol: `RT7272BGSP`-- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm` - 3D model: SOIC-8-EP (KiCad packages3D, STEP) ## Provenance
rt7272bgsp.kicad_mod+13−13@@ -1,8 +1,8 @@-(footprint "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm"+(footprint "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm" (version 20260206) (generator "kicad-footprint-generator") (layer "F.Cu")- (descr "SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29)")+ (descr "SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8)") (tags "SOIC SO") (property "Reference" "REF**" (at 0 -3.4 0)@@ -14,7 +14,7 @@ ) ) )- (property "Value" "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm"+ (property "Value" "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm" (at 0 3.4 0) (layer "F.Fab") (effects@@ -238,26 +238,26 @@ ) ) (pad "" smd roundrect- (at -0.57 -0.75)- (size 0.92 1.21)+ (at -0.6 -0.825)+ (size 0.97 1.33) (layers "F.Paste") (roundrect_rratio 0.25) ) (pad "" smd roundrect- (at -0.57 0.75)- (size 0.92 1.21)+ (at -0.6 0.825)+ (size 0.97 1.33) (layers "F.Paste") (roundrect_rratio 0.25) ) (pad "" smd roundrect- (at 0.57 -0.75)- (size 0.92 1.21)+ (at 0.6 -0.825)+ (size 0.97 1.33) (layers "F.Paste") (roundrect_rratio 0.25) ) (pad "" smd roundrect- (at 0.57 0.75)- (size 0.92 1.21)+ (at 0.6 0.825)+ (size 0.97 1.33) (layers "F.Paste") (roundrect_rratio 0.25) )@@ -311,13 +311,13 @@ ) (pad "9" smd rect (at 0 0)- (size 2.29 3)+ (size 2.41 3.3) (property pad_prop_heatsink) (layers "F.Cu" "F.Mask") (zone_connect 2) ) (embedded_fonts no)- (model "${KICAD10_3DMODEL_DIR}/Package_SO.3dshapes/SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.step"+ (model "${KICAD10_3DMODEL_DIR}/Package_SO.3dshapes/SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.step" (offset (xyz 0 0 0) )
rt7272bgsp.lbr+1−1@@ -62,7 +62,7 @@ <smd name="6" x="2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>- <smd name="9" x="0.0000" y="-0.0000" dx="2.2900" dy="3.0000" layer="1"/>+ <smd name="9" x="0.0000" y="-0.0000" dx="2.4100" dy="3.3000" layer="1"/> <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>