component
RT7272BGSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C127866). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+26−6
page.json+4−2@@ -26,7 +26,9 @@ "model_3d_step": "rt7272bgsp.step", "lbr": "rt7272bgsp.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C127866"+ }, "pins": [ { "number": "1",@@ -44,7 +46,7 @@ "number": "3", "name": "EN", "type": "input",- "description": "Enable Control Input. Logic-high (VIH ≥ 2V) enables the converter; logic-low (VIL ≤ 0.4V) forces the device into shutdown mode (IQ ≈ 0.5µA). Do not float."+ "description": "Enable Control Input. Logic-high (VIH \u2265 2V) enables the converter; logic-low (VIL \u2264 0.4V) forces the device into shutdown mode (IQ \u2248 0.5\u00b5A). Do not float." }, { "number": "4",
rt7272bgsp.lbr+22−4@@ -63,6 +63,18 @@ <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/> <smd name="9" x="0.0000" y="-0.0000" dx="2.4100" dy="3.3000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.6000" y="2.4700"/>+ <vertex x="-2.8400" y="2.8000"/>+ <vertex x="-2.3600" y="2.8000"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.9750" y="2.4500"/>+ <vertex x="1.9500" y="2.4500"/>+ <vertex x="1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="1.4750"/>+ </polygon> <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -71,7 +83,7 @@ <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/> <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="RT7272BGSP">@@ -86,7 +98,7 @@ <pin name="EN" x="-17.78" y="0" length="middle" direction="in"/> <pin name="GND" x="-17.78" y="-2.54" length="middle" direction="pwr"/> <pin name="FB" x="-17.78" y="-5.08" length="middle" direction="in"/>- <pin name="GND (Exposed Pad)" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="GND_Exposed_Pad" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/> <pin name="VIN" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/> <pin name="RLIM" x="17.78" y="-2.54" length="middle" direction="in" rot="R180"/> <pin name="COMP" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/>@@ -106,12 +118,18 @@ <connect gate="G$1" pin="EN" pad="3"/> <connect gate="G$1" pin="GND" pad="4"/> <connect gate="G$1" pin="FB" pad="5"/>- <connect gate="G$1" pin="GND (Exposed Pad)" pad="9"/>+ <connect gate="G$1" pin="GND_Exposed_Pad" pad="9"/> <connect gate="G$1" pin="VIN" pad="8"/> <connect gate="G$1" pin="RLIM" pad="7"/> <connect gate="G$1" pin="COMP" pad="6"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="RT7272BGSP" constant="no"/>+ <attribute name="MANUFACTURER" value="Richtek Tech" constant="no"/>+ <attribute name="LCSC_PN" value="C127866" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>