component
RS0108YQ20
Public Made by Adomby adom
Jiangsu RUNIC Tech Translators / Level Shifters, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C2762289). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+26−6
page.json+6−4@@ -26,7 +26,9 @@ "model_3d_step": "rs0108yq20.step", "lbr": "rs0108yq20.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C2762289"+ }, "pins": [ { "number": "1",@@ -38,7 +40,7 @@ "number": "2", "name": "VCCA", "type": "power_in",- "description": "A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V and VCCA ≤ VCCB. Sets the A-side logic reference for pins A1-A8 and OE."+ "description": "A-port supply voltage. 1.65 V \u2264 VCCA \u2264 5.5 V and VCCA \u2264 VCCB. Sets the A-side logic reference for pins A1-A8 and OE." }, { "number": "3",@@ -86,7 +88,7 @@ "number": "10", "name": "OE", "type": "input",- "description": "Output Enable, active high. Referenced to VCCA (VIH ≥ 0.8·VCCA). Drive OE low to place all I/Os in the high-impedance 3-state; tie to GND through a pull-down resistor to guarantee Hi-Z during power-up/down. Internal pull-down current source is present when VCCA is powered."+ "description": "Output Enable, active high. Referenced to VCCA (VIH \u2265 0.8\u00b7VCCA). Drive OE low to place all I/Os in the high-impedance 3-state; tie to GND through a pull-down resistor to guarantee Hi-Z during power-up/down. Internal pull-down current source is present when VCCA is powered." }, { "number": "11",@@ -140,7 +142,7 @@ "number": "19", "name": "VCCB", "type": "power_in",- "description": "B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V and VCCB ≥ VCCA. Sets the B-side logic reference for pins B1-B8."+ "description": "B-port supply voltage. 2.3 V \u2264 VCCB \u2264 5.5 V and VCCB \u2265 VCCA. Sets the B-side logic reference for pins B1-B8." }, { "number": "20",
rs0108yq20.lbr+20−2@@ -74,11 +74,23 @@ <smd name="18" x="2.8625" y="1.6250" dx="1.4750" dy="0.4000" layer="1"/> <smd name="19" x="2.8625" y="2.2750" dx="1.4750" dy="0.4000" layer="1"/> <smd name="20" x="2.8625" y="2.9250" dx="1.4750" dy="0.4000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-3.8600" y="2.9300"/>+ <vertex x="-4.1900" y="2.6900"/>+ <vertex x="-4.1900" y="3.1700"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-1.2000" y="3.2500"/>+ <vertex x="2.2000" y="3.2500"/>+ <vertex x="2.2000" y="-3.2500"/>+ <vertex x="-2.2000" y="-3.2500"/>+ <vertex x="-2.2000" y="2.2500"/>+ </polygon> <wire x1="-2.3100" y1="3.3850" x2="2.3100" y2="3.3850" width="0.1200" layer="21"/> <wire x1="2.3100" y1="-3.3850" x2="-2.3100" y2="-3.3850" width="0.1200" layer="21"/> <text x="0" y="4.262" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-4.262" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-3.8600" y="2.9300"/><vertex x="-4.1900" y="2.6900"/><vertex x="-4.1900" y="3.1700"/></polygon></package>+</package> </packages> <symbols> <symbol name="RS0108YQ20">@@ -140,7 +152,13 @@ <connect gate="G$1" pin="B8" pad="12"/> <connect gate="G$1" pin="GND" pad="11"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="RS0108YQ20" constant="no"/>+ <attribute name="MANUFACTURER" value="Jiangsu RUNIC Tech" constant="no"/>+ <attribute name="LCSC_PN" value="C2762289" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>