component
RP2350A
Public Made by Adomby adom
Raspberry Pi Microcontrollers, QFN-60-EP(7x7). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.
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package.jsonadded+492@@ -0,0 +1,492 @@+{+ "slug": "rp2350a",+ "version": "0.1.0",+ "type": "component",+ "tags": [+ "component",+ "embedded processors & controllers",+ "rp2350a",+ "board-derived",+ "staged-for-validation"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "verification.json",+ "rp2350a.kicad_sym",+ "rp2350a.kicad_mod",+ "rp2350a-etched.glb",+ "rp2350a-etched.step",+ "rp2350a.glb",+ "rp2350a.step",+ "rp2350a.lbr",+ "docs/hero.png",+ "docs/rp2350a-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "RP2350A",+ "manufacturer": "Raspberry Pi",+ "package": "QFN-60-EP(7x7)",+ "pin_count": 61,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8562345067823054848",+ "parts": {+ "symbol": "rp2350a.kicad_sym",+ "footprint": "rp2350a.kicad_mod",+ "model_3d": "rp2350a-etched.glb",+ "model_3d_plain": "rp2350a.glb",+ "model_3d_step": "rp2350a-etched.step",+ "model_3d_step_plain": "rp2350a.step",+ "lbr": "rp2350a.lbr"+ },+ "distributor_links": {+ "digikey": false,+ "digikey_note": "2026-10-08: no exact-MPN listing for RP2350A found via the digikey API.",+ "mouser": false,+ "mouser_note": "2026-10-08: no exact-MPN listing for RP2350A found via the mouser API.",+ "lcsc": {+ "part": "C42411118",+ "url": "https://www.lcsc.com/product-detail/C42411118.html"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1332]"+ },+ {+ "number": "2",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Default drive 4 mA; programmable pull-up/pull-down, slew rate, Schmitt trigger. Reset state: pull-down. Muxable to SPI0_RX / UART0_TX / I2C0_SDA / PWM0_A / SIO / PIO0..2 / QMI_CS1n / USB OVCUR DET. [datasheet p.1328]"+ },+ {+ "number": "3",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_CSn / UART0_RX / I2C0_SCL / PWM0_B / SIO / PIO0..2 / TRACECLK / USB VBUS DET. [datasheet p.1328]"+ },+ {+ "number": "4",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_SCK / UART0_CTS / I2C1_SDA / PWM1_A / SIO / PIO0..2 / TRACEDATA0 / USB VBUS EN / UART0_TX. [datasheet p.1328]"+ },+ {+ "number": "5",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_TX / UART0_RTS / I2C1_SCL / PWM1_B / SIO / PIO0..2 / TRACEDATA1 / USB OVCUR DET / UART0_RX. [datasheet p.1328]"+ },+ {+ "number": "6",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital core supply, nominal 1.1 V. Must be driven externally — either from the on-chip VREG output (VREG_LX filtered to DVDD) or from an off-chip 1.1 V rail. One of three DVDD pins (also pins 23, 39). [datasheet p.1332]"+ },+ {+ "number": "7",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_RX / UART1_TX / I2C0_SDA / PWM2_A / SIO / PIO0..2 / TRACEDATA2 / USB VBUS DET. [datasheet p.1328]"+ },+ {+ "number": "8",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_CSn / UART1_RX / I2C0_SCL / PWM2_B / SIO / PIO0..2 / TRACEDATA3 / USB VBUS EN. [datasheet p.1328]"+ },+ {+ "number": "9",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_SCK / UART1_CTS / I2C1_SDA / PWM3_A / SIO / PIO0..2 / USB OVCUR DET / UART1_TX. [datasheet p.1328]"+ },+ {+ "number": "10",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_TX / UART1_RTS / I2C1_SCL / PWM3_B / SIO / PIO0..2 / USB VBUS DET / UART1_RX. [datasheet p.1328]"+ },+ {+ "number": "11",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1332]"+ },+ {+ "number": "12",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_RX / UART1_TX / I2C0_SDA / PWM4_A / SIO / PIO0..2 / QMI_CS1n / USB VBUS EN. [datasheet p.1328]"+ },+ {+ "number": "13",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_CSn / UART1_RX / I2C0_SCL / PWM4_B / SIO / PIO0..2 / USB OVCUR DET. [datasheet p.1328]"+ },+ {+ "number": "14",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_SCK / UART1_CTS / I2C1_SDA / PWM5_A / SIO / PIO0..2 / USB VBUS DET / UART1_TX. [datasheet p.1328]"+ },+ {+ "number": "15",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_TX / UART1_RTS / I2C1_SCL / PWM5_B / SIO / PIO0..2 / USB VBUS EN / UART1_RX. [datasheet p.1328]"+ },+ {+ "number": "16",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_RX / UART0_TX / I2C0_SDA / PWM6_A / SIO / PIO0..2 / CLOCK GPIN0 / USB OVCUR DET. [datasheet p.1328]"+ },+ {+ "number": "17",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_CSn / UART0_RX / I2C0_SCL / PWM6_B / SIO / PIO0..2 / CLOCK GPOUT0 / USB VBUS DET. [datasheet p.1328]"+ },+ {+ "number": "18",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_SCK / UART0_CTS / I2C1_SDA / PWM7_A / SIO / PIO0..2 / CLOCK GPIN1 / USB VBUS EN / UART0_TX. [datasheet p.1328]"+ },+ {+ "number": "19",+ "name": "GPIO15",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI1_TX / UART0_RTS / I2C1_SCL / PWM7_B / SIO / PIO0..2 / CLOCK GPOUT1 / USB OVCUR DET / UART0_RX. [datasheet p.1328]"+ },+ {+ "number": "20",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1332]"+ },+ {+ "number": "21",+ "name": "XIN",+ "type": "input",+ "description": "Crystal oscillator input. Attach a crystal (typically 12 MHz for the stock USB bootloader) between XIN and XOUT with the recommended load capacitors; or drive XIN with a square-wave CMOS clock (0.65*IOVDD to IOVDD+0.3 V high) with XOUT left floating. XOSC input range 1-50 MHz. [datasheet p.1331]"+ },+ {+ "number": "22",+ "name": "XOUT",+ "type": "passive",+ "description": "Crystal oscillator output. Connect to the far side of the crystal with load capacitor to ground. Leave floating when XIN is driven by an external clock. [datasheet p.1331]"+ },+ {+ "number": "23",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital core supply, nominal 1.1 V. Must be driven externally — either from the on-chip VREG output (VREG_LX filtered to DVDD) or from an off-chip 1.1 V rail. One of three DVDD pins (also pins 23, 39). [datasheet p.1332]"+ },+ {+ "number": "24",+ "name": "SWCLK",+ "type": "output",+ "description": "Serial Wire Debug clock input (Fault-Tolerant). Pull-up at reset. SWD operates reliably up to 50 MHz on-chip (external signal integrity may limit practical rate). [datasheet p.1331]"+ },+ {+ "number": "25",+ "name": "SWD",+ "type": "bidirectional",+ "description": ""+ },+ {+ "number": "26",+ "name": "RUN",+ "type": "input",+ "description": "Global asynchronous active-low reset input (Fault-Tolerant). Drive low to hold chip in reset; release high to run. Pull-up at reset. If no external reset is needed, tie directly to IOVDD. [datasheet p.1331]"+ },+ {+ "number": "27",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_RX / UART0_TX / I2C0_SDA / PWM0_A / SIO / PIO0..2 / USB VBUS DET. [datasheet p.1328]"+ },+ {+ "number": "28",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_CSn / UART0_RX / I2C0_SCL / PWM0_B / SIO / PIO0..2 / USB VBUS EN. [datasheet p.1328]"+ },+ {+ "number": "29",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_SCK / UART0_CTS / I2C1_SDA / PWM1_A / SIO / PIO0..2 / USB OVCUR DET / UART0_TX. [datasheet p.1328]"+ },+ {+ "number": "30",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1332]"+ },+ {+ "number": "31",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to HSTX / SPI0_TX / UART0_RTS / I2C1_SCL / PWM1_B / SIO / PIO0..2 / QMI_CS1n / USB VBUS DET / UART0_RX. [datasheet p.1328]"+ },+ {+ "number": "32",+ "name": "GPIO20",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_RX / UART1_TX / I2C0_SDA / PWM2_A / SIO / PIO0..2 / CLOCK GPIN0 / USB VBUS EN. [datasheet p.1328]"+ },+ {+ "number": "33",+ "name": "GPIO21",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_CSn / UART1_RX / I2C0_SCL / PWM2_B / SIO / PIO0..2 / CLOCK GPOUT0 / USB OVCUR DET. [datasheet p.1328]"+ },+ {+ "number": "34",+ "name": "GPIO22",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_SCK / UART1_CTS / I2C1_SDA / PWM3_A / SIO / PIO0..2 / CLOCK GPIN1 / USB VBUS DET / UART1_TX. [datasheet p.1328]"+ },+ {+ "number": "35",+ "name": "GPIO23",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI0_TX / UART1_RTS / I2C1_SCL / PWM3_B / SIO / PIO0..2 / CLOCK GPOUT1 / USB VBUS EN / UART1_RX. [datasheet p.1328]"+ },+ {+ "number": "36",+ "name": "GPIO24",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_RX / UART1_TX / I2C0_SDA / PWM4_A / SIO / PIO0..2 / CLOCK GPOUT2 / USB OVCUR DET. [datasheet p.1328]"+ },+ {+ "number": "37",+ "name": "GPIO25",+ "type": "bidirectional",+ "description": "General-purpose Fault-Tolerant digital IO (Bank 0). Reset state: pull-down. Muxable to SPI1_CSn / UART1_RX / I2C0_SCL / PWM4_B / SIO / PIO0..2 / CLOCK GPOUT3 / USB VBUS DET. [datasheet p.1328]"+ },+ {+ "number": "38",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1332]"+ },+ {+ "number": "39",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital core supply, nominal 1.1 V. Must be driven externally — either from the on-chip VREG output (VREG_LX filtered to DVDD) or from an off-chip 1.1 V rail. One of three DVDD pins (also pins 23, 39). [datasheet p.1332]"+ },+ {+ "number": "40",+ "name": "GPIO26_ADC0",+ "type": "bidirectional",+ "description": "GPIO26 or ADC channel 0 input. Digital IO + Analogue input domain (IOVDD / ADC_AVDD). Full ADC range 0 V to ADC_AVDD (nominal 3.3 V). 12-bit SAR ADC, 100 kΩ input impedance; keep input ≤ IOVDD to avoid ESD-diode leakage. [datasheet p.1328]"+ },+ {+ "number": "41",+ "name": "GPIO27_ADC1",+ "type": "bidirectional",+ "description": "GPIO27 or ADC channel 1 input. Digital IO + Analogue input. Same characteristics as ADC0: 12-bit, 0 V to ADC_AVDD. [datasheet p.1328]"+ },+ {+ "number": "42",+ "name": "GPIO28_ADC2",+ "type": "bidirectional",+ "description": "GPIO28 or ADC channel 2 input. Digital IO + Analogue input. 12-bit SAR, 0 V to ADC_AVDD. [datasheet p.1328]"+ },+ {+ "number": "43",+ "name": "GPIO29_ADC3",+ "type": "bidirectional",+ "description": "GPIO29 or ADC channel 3 input. Digital IO + Analogue input. 12-bit SAR, 0 V to ADC_AVDD. [datasheet p.1328]"+ },+ {+ "number": "44",+ "name": "ADC_AVDD",+ "type": "power_in",+ "description": "Analogue supply for the ADC and reference. Nominal 3.3 V. Must be powered whenever any ADC input is used. Low-noise bulk/decoupling recommended; can share source with VREG_AVDD/IOVDD at 3.3 V with filtering. [datasheet p.1332]"+ },+ {+ "number": "45",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Power supply for digital GPIOs (Bank 0 IO voltage). Nominal 1.8 V to 3.3 V. Bulk/decoupling required. [datasheet p.1332]"+ },+ {+ "number": "46",+ "name": "VREG_AVDD",+ "type": "power_in",+ "description": "Analogue supply for the on-chip core voltage regulator and power-on-reset / brownout detection. Nominal 3.3 V. Must be powered even when the regulator is disabled. Can share source with VREG_VIN or IOVDD at 3.3 V, with careful decoupling. [datasheet p.1332]"+ },+ {+ "number": "47",+ "name": "VREG_PGND",+ "type": "power_in",+ "description": "Power ground return for the internal switched-mode core voltage regulator. Tie externally to the main GND plane (dedicated short/low-impedance path recommended because switcher currents flow here). [datasheet p.1332]"+ },+ {+ "number": "48",+ "name": "VREG_LX",+ "type": "power_out",+ "description": "Switching-node output of the on-chip buck regulator. Connect to the external inductor of the buck filter network (inductor + output capacitor to GND, feedback to VREG_FB). Nominal 1.1 V after LC filtering; max 200 mA. [datasheet p.1332]"+ },+ {+ "number": "49",+ "name": "VREG_VIN",+ "type": "power_in",+ "description": "Input supply for the internal core voltage regulator (both buck and low-quiescent LDO modes). Range 2.7 V to 5.5 V. Bulk + ceramic decoupling at the pin. [datasheet p.1332]"+ },+ {+ "number": "50",+ "name": "VREG_FB",+ "type": "input",+ "description": "Feedback input for the on-chip core voltage regulator. Connect to the filtered regulator output (typically DVDD) so the regulator senses the actual core voltage after the inductor and output cap. [datasheet p.1332]"+ },+ {+ "number": "51",+ "name": "USB_DM",+ "type": "bidirectional",+ "description": "USB 1.1 Full/Low Speed D- signal. External 27 Ω series termination required for USB operation. Internal pull-ups/pull-downs are provided per the USB spec. May be reused as a software-controlled GPIO when USB is not used. [datasheet p.1331]"+ },+ {+ "number": "52",+ "name": "USB_DP",+ "type": "bidirectional",+ "description": "USB 1.1 Full/Low Speed D+ signal. External 27 Ω series termination required for USB operation. Powered by USB_OTP_VDD. [datasheet p.1331]"+ },+ {+ "number": "53",+ "name": "USB_OTP_VDD",+ "type": "power_in",+ "description": "Supply rail for the on-chip USB Full-Speed PHY and OTP storage. Nominal 3.3 V. Decouple close to the pin; USB_DP/USB_DM referenced to this rail. [datasheet p.1332]"+ },+ {+ "number": "54",+ "name": "QSPI_IOVDD",+ "type": "power_in",+ "description": "Supply for the dedicated QSPI IO pads (QSPI_SS, QSPI_SCLK, QSPI_SD0..3). Nominal 1.8 V to 3.3 V (2.7-3.6 V when driving an internal flash die in RP2354A). Must match the external flash/PSRAM Vcc. [datasheet p.1332]"+ },+ {+ "number": "55",+ "name": "QSPI_SD3",+ "type": "bidirectional",+ "description": "QSPI data line 3 (dedicated XIP interface). Pull-up at reset. In single-SPI mode this doubles as /HOLD or /RESET on standard NOR flash. May be used as a software-controlled GPIO if the QSPI bus is not used. [datasheet p.1331]"+ },+ {+ "number": "56",+ "name": "QSPI_SCLK",+ "type": "output",+ "description": "QSPI clock output to external flash/PSRAM (and internal flash die in RP2354A). Pull-down at reset. Max 133 MHz when paired with W25Q16JV. [datasheet p.1331]"+ },+ {+ "number": "57",+ "name": "QSPI_SD0",+ "type": "bidirectional",+ "description": "QSPI data line 0 (MOSI in single-SPI mode). Pull-down at reset. [datasheet p.1331]"+ },+ {+ "number": "58",+ "name": "QSPI_SD2",+ "type": "bidirectional",+ "description": "QSPI data line 2. In single-SPI mode doubles as /WP on standard NOR flash. Pull-up at reset. [datasheet p.1331]"+ },+ {+ "number": "59",+ "name": "QSPI_SD1",+ "type": "bidirectional",+ "description": "QSPI data line 1 (MISO in single-SPI mode). Pull-down at reset. If held high while QSPI_SS is low on power-up, selects UART-boot BOOTSEL mode (UART TX on SD2, RX on SD3). [datasheet p.1331]"+ },+ {+ "number": "60",+ "name": "QSPI_SS",+ "type": "bidirectional",+ "description": "QSPI chip-select (active low). Pull-up at reset. If held low during reset the chip enters BOOTSEL mode (USB mass-storage/UART boot). Supports an external second QSPI device via a secondary CSn from Bank 0. [datasheet p.1331]"+ },+ {+ "number": "61",+ "name": "GND",+ "type": "power_in",+ "description": "Central exposed pad — single external ground connection, bonded to all internal ground pads. Must be soldered to the PCB ground plane for proper electrical operation and thermal conduction (θJB ≈ 12.6 °C/W). [datasheet p.1332]"+ }+ ],+ "provenance": {+ "factory_chain": {+ "pipeline": "adom-parts (board-derived) 0.1",+ "pins": "KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7)",+ "at": "2026-10-08"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8562345067823054848",+ "pages": 1357,+ "sha256": "78e209ff6a40a8a7ecc750488a9065f61d962f607404ae6731b5192c9fef3cc1",+ "source_tier": "lcsc"+ },+ "cad": "Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export",+ "pins": {+ "total": 61,+ "described": 60,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "rp2350a.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin",+ "seat": "z = 0 (PCB top surface)",+ "extents_mm": [+ 7.002,+ 7.002,+ 0.86+ ],+ "zmin_mm": -0.0,+ "footprint_binding": "identity",+ "sha256": "675e2cf0b38f0ad06df235f63ea178043f4c4c1ccd1779b33b0d6e6f47d35b22",+ "checked": "2026-10-08",+ "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+ },+ {+ "file": "rp2350a-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin",+ "seat": "z = 0 (PCB top surface)",+ "extents_mm": [+ 7.002,+ 7.002,+ 0.862+ ],+ "zmin_mm": -0.0,+ "footprint_binding": "identity",+ "sha256": "d95f3bac33a466ec114db2a03d4cb11f5f2dcc8c006a5032b4c71c8d718a3563",+ "checked": "2026-10-08",+ "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+ }+ ]+ },+ "description": "Raspberry Pi Microcontrollers, QFN-60-EP(7x7). KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet."+}