component
PT7M3808G01TAEX
Public Made by Adomby adom
Diodes Incorporated Supervisor and Reset ICs, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+9−6@@ -32,7 +32,7 @@ "number": "1", "name": "RESET", "type": "output",- "description": "Active-low, open-drain RESET output. Driven to a low-impedance state when reset is asserted and remains asserted for the programmed delay after both SENSE rises above VIT and MR returns high. Requires an external pull-up (10k\u03a9 to 1M\u03a9); the pull-up may be tied to a rail higher than VDD (up to 6.5V). Guaranteed VOL 0.3V @ IOL=0.4mA (1.3V<=VDD<1.8V) or 0.4V @ IOL=1.0mA (1.8V<=VDD<=6.5V); leakage <=300nA when not asserted."+ "description": "Active-low, open-drain RESET output. Driven to a low-impedance state when reset is asserted and remains asserted for the programmed delay after both SENSE rises above VIT and MR returns high. Requires an external pull-up (10kΩ to 1MΩ); the pull-up may be tied to a rail higher than VDD (up to 6.5V). Guaranteed VOL 0.3V @ IOL=0.4mA (1.3V<=VDD<1.8V) or 0.4V @ IOL=1.0mA (1.8V<=VDD<=6.5V); leakage <=300nA when not asserted." }, { "number": "2",@@ -44,25 +44,25 @@ "number": "3", "name": "MR", "type": "input",- "description": "Active-low manual reset input. Driving MR below 0.3*VDD asserts RESET; MR must return above 0.7*VDD to clear. Internally pulled up to VDD by a ~90k\u03a9 (70k min) resistor, so the pin can be left floating if unused. Do not apply voltage above VDD."+ "description": "Active-low manual reset input. Driving MR below 0.3*VDD asserts RESET; MR must return above 0.7*VDD to clear. Internally pulled up to VDD by a ~90kΩ (70k min) resistor, so the pin can be left floating if unused. Do not apply voltage above VDD." }, { "number": "4", "name": "CT", "type": "passive",- "description": "Reset-delay programming pin. Three modes: (a) leave open -> fixed 20ms delay; (b) tie to VDD through 40k-200k\u03a9 -> fixed 300ms delay; (c) tie an external capacitor (>=100pF) from CT to GND -> user-programmable delay 1.25ms-10s per CT(nF)=[tD(s)-0.5e-3]x175. Charged by an internal 220nA source to 1.23V. Absolute range -0.3V to VDD+0.5V; use low-leakage (ceramic) capacitors."+ "description": "Reset-delay programming pin. Three modes: (a) leave open -> fixed 20ms delay; (b) tie to VDD through 40k-200kΩ -> fixed 300ms delay; (c) tie an external capacitor (>=100pF) from CT to GND -> user-programmable delay 1.25ms-10s per CT(nF)=[tD(s)-0.5e-3]x175. Charged by an internal 220nA source to 1.23V. Absolute range -0.3V to VDD+0.5V; use low-leakage (ceramic) capacitors." }, { "number": "5", "name": "SENSE", "type": "input",- "description": "Voltage-monitor input. RESET asserts when SENSE drops below the negative-going threshold VIT (0.405V typ on the G01 adjustable variant); the comparator has ~1.5% VIT hysteresis. Input current \u00b125nA max on G01. Recommended to add a 1nF-10nF bypass capacitor for noise immunity. Absolute range -0.3V to +7V."+ "description": "Voltage-monitor input. RESET asserts when SENSE drops below the negative-going threshold VIT (0.405V typ on the G01 adjustable variant); the comparator has ~1.5% VIT hysteresis. Input current ±25nA max on G01. Recommended to add a 1nF-10nF bypass capacitor for noise immunity. Absolute range -0.3V to +7V." }, { "number": "6", "name": "VDD", "type": "power_in",- "description": "Supply voltage, 1.7V to 6.5V (absolute max 7.0V). Typical quiescent current ~2.8\u00b5A at 3.3V. Place a 0.1\u00b5F ceramic decoupling capacitor close to this pin."+ "description": "Supply voltage, 1.7V to 6.5V (absolute max 7.0V). Typical quiescent current ~2.8µA at 3.3V. Place a 0.1µF ceramic decoupling capacitor close to this pin." } ], "provenance": {@@ -126,5 +126,8 @@ "docs/pt7m3808g01taex-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }