PT7M3808G01TAEX

@@ -26,13 +26,15 @@       "model_3d_step": "pt7m3808g01taex.step",       "lbr": "pt7m3808g01taex.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C780887"+    },     "pins": [       {         "number": "1",         "name": "RESET",         "type": "output",-        "description": "Active-low, open-drain RESET output. Driven to a low-impedance state when reset is asserted and remains asserted for the programmed delay after both SENSE rises above VIT and MR returns high. Requires an external pull-up (10kΩ to 1MΩ); the pull-up may be tied to a rail higher than VDD (up to 6.5V). Guaranteed VOL 0.3V @ IOL=0.4mA (1.3V<=VDD<1.8V) or 0.4V @ IOL=1.0mA (1.8V<=VDD<=6.5V); leakage <=300nA when not asserted."+        "description": "Active-low, open-drain RESET output. Driven to a low-impedance state when reset is asserted and remains asserted for the programmed delay after both SENSE rises above VIT and MR returns high. Requires an external pull-up (10k\u03a9 to 1M\u03a9); the pull-up may be tied to a rail higher than VDD (up to 6.5V). Guaranteed VOL 0.3V @ IOL=0.4mA (1.3V<=VDD<1.8V) or 0.4V @ IOL=1.0mA (1.8V<=VDD<=6.5V); leakage <=300nA when not asserted."       },       {         "number": "2",@@ -44,25 +46,25 @@         "number": "3",         "name": "MR",         "type": "input",-        "description": "Active-low manual reset input. Driving MR below 0.3*VDD asserts RESET; MR must return above 0.7*VDD to clear. Internally pulled up to VDD by a ~90kΩ (70k min) resistor, so the pin can be left floating if unused. Do not apply voltage above VDD."+        "description": "Active-low manual reset input. Driving MR below 0.3*VDD asserts RESET; MR must return above 0.7*VDD to clear. Internally pulled up to VDD by a ~90k\u03a9 (70k min) resistor, so the pin can be left floating if unused. Do not apply voltage above VDD."       },       {         "number": "4",         "name": "CT",         "type": "passive",-        "description": "Reset-delay programming pin. Three modes: (a) leave open -> fixed 20ms delay; (b) tie to VDD through 40k-200kΩ -> fixed 300ms delay; (c) tie an external capacitor (>=100pF) from CT to GND -> user-programmable delay 1.25ms-10s per CT(nF)=[tD(s)-0.5e-3]x175. Charged by an internal 220nA source to 1.23V. Absolute range -0.3V to VDD+0.5V; use low-leakage (ceramic) capacitors."+        "description": "Reset-delay programming pin. Three modes: (a) leave open -> fixed 20ms delay; (b) tie to VDD through 40k-200k\u03a9 -> fixed 300ms delay; (c) tie an external capacitor (>=100pF) from CT to GND -> user-programmable delay 1.25ms-10s per CT(nF)=[tD(s)-0.5e-3]x175. Charged by an internal 220nA source to 1.23V. Absolute range -0.3V to VDD+0.5V; use low-leakage (ceramic) capacitors."       },       {         "number": "5",         "name": "SENSE",         "type": "input",-        "description": "Voltage-monitor input. RESET asserts when SENSE drops below the negative-going threshold VIT (0.405V typ on the G01 adjustable variant); the comparator has ~1.5% VIT hysteresis. Input current ±25nA max on G01. Recommended to add a 1nF-10nF bypass capacitor for noise immunity. Absolute range -0.3V to +7V."+        "description": "Voltage-monitor input. RESET asserts when SENSE drops below the negative-going threshold VIT (0.405V typ on the G01 adjustable variant); the comparator has ~1.5% VIT hysteresis. Input current \u00b125nA max on G01. Recommended to add a 1nF-10nF bypass capacitor for noise immunity. Absolute range -0.3V to +7V."       },       {         "number": "6",         "name": "VDD",         "type": "power_in",-        "description": "Supply voltage, 1.7V to 6.5V (absolute max 7.0V). Typical quiescent current ~2.8µA at 3.3V. Place a 0.1µF ceramic decoupling capacitor close to this pin."+        "description": "Supply voltage, 1.7V to 6.5V (absolute max 7.0V). Typical quiescent current ~2.8\u00b5A at 3.3V. Place a 0.1\u00b5F ceramic decoupling capacitor close to this pin."       }     ],     "provenance": {

@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="PT7M3808G01TAEX">@@ -102,7 +114,13 @@         <connect gate="G$1" pin="SENSE" pad="5"/>         <connect gate="G$1" pin="CT" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="PT7M3808G01TAEX" constant="no"/>+          <attribute name="MANUFACTURER" value="Diodes Incorporated" constant="no"/>+          <attribute name="LCSC_PN" value="C780887" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>