component
PIC16F77-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+141@@ -0,0 +1,141 @@+# PIC16F77-I++**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)++PIC16F77-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RC7/RX/DT | bidirectional | Digital I/O (Schmitt Trigger input) that serves as USART asynchronous receive input (RX) or USART synchronous data I/O (DT). |+| 2 | RD4/PSP4 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 4 (PSP4). |+| 3 | RD5/PSP5 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 5 (PSP5). |+| 4 | RD6/PSP6 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 6 (PSP6). |+| 5 | RD7/PSP7 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 7 (PSP7). |+| 6 | VSS | power_in | Ground reference for logic and I/O pins. |+| 7 | VDD | power_in | Positive supply for logic and I/O pins. |+| 8 | RB0/INT | bidirectional | Digital I/O (TTL/Schmitt Trigger when used as external interrupt) that serves as external interrupt input INT; PORTB has software-programmable weak pull-up. |+| 9 | RB1 | bidirectional | Digital I/O (TTL) with software-programmable PORTB weak pull-up. |+| 10 | RB2 | bidirectional | Digital I/O (TTL) with software-programmable PORTB weak pull-up. |+| 11 | RB3/PGM | bidirectional | Digital I/O (TTL) that serves as low-voltage ICSP programming enable pin (PGM). |+| 12 | NC | unconnected | Not internally connected; these pins should be left unconnected. |+| 13 | NC | unconnected | Not internally connected; these pins should be left unconnected. |+| 14 | RB4 | bidirectional | Digital I/O (TTL) with software-programmable PORTB weak pull-up. |+| 15 | RB5 | bidirectional | Digital I/O (TTL) with software-programmable PORTB weak pull-up. |+| 16 | RB6/PGC | bidirectional | Digital I/O (TTL/Schmitt Trigger in serial programming mode) that serves as In-Circuit Debugger and ICSP programming clock (PGC). |+| 17 | RB7/PGD | bidirectional | Digital I/O (TTL/Schmitt Trigger in serial programming mode) that serves as In-Circuit Debugger and ICSP programming data (PGD). |+| 18 | MCLR/VPP | input | Active-low master clear (Reset) input to the device, or programming voltage input (VPP). |+| 19 | RA0/AN0 | bidirectional | Digital I/O (TTL) that also serves as analog input 0 (AN0). |+| 20 | RA1/AN1 | bidirectional | Digital I/O (TTL) that also serves as analog input 1 (AN1). |+| 21 | RA2/AN2 | bidirectional | Digital I/O (TTL) that also serves as analog input 2 (AN2). |+| 22 | RA3/AN3/VREF | bidirectional | Digital I/O (TTL) that also serves as analog input 3 (AN3) and A/D reference voltage input (VREF). |+| 23 | RA4/T0CKI | bidirectional | Digital I/O (Schmitt Trigger input, open drain when configured as output) that serves as Timer0 external clock input (T0CKI). |+| 24 | RA5/SS/AN4 | bidirectional | Digital I/O (TTL) that serves as SPI slave select input (SS) and analog input 4 (AN4). |+| 25 | RE0/RD/AN5 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port read control (RD) and analog input 5 (AN5). |+| 26 | RE1/WR/AN6 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port write control (WR) and analog input 6 (AN6). |+| 27 | RE2/CS/AN7 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port chip select control (CS) and analog input 7 (AN7). |+| 28 | VDD | power_in | Positive supply for logic and I/O pins. |+| 29 | VSS | power_in | Ground reference for logic and I/O pins. |+| 30 | OSC1/CLKI | input | Oscillator crystal input or external clock source input (ST buffer in RC mode, otherwise CMOS). |+| 31 | OSC2/CLKO | output | Oscillator crystal output for crystal/resonator mode; in RC mode outputs CLKO at 1/4 the frequency of OSC1. |+| 32 | RC0/T1OSO/T1CKI | bidirectional | Digital I/O (Schmitt Trigger input) that serves as Timer1 oscillator output (T1OSO) and Timer1 external clock input (T1CKI). |+| 33 | NC | unconnected | Not internally connected; these pins should be left unconnected. |+| 34 | NC | unconnected | Not internally connected; these pins should be left unconnected. |+| 35 | RC1/T1OSI/CCP2 | bidirectional | Digital I/O (Schmitt Trigger input) that serves as Timer1 oscillator input (T1OSI) and Capture2 input/Compare2 output/PWM2 output (CCP2). |+| 36 | RC2/CCP1 | bidirectional | Digital I/O (Schmitt Trigger input) that serves as Capture1 input/Compare1 output/PWM1 output (CCP1). |+| 37 | RC3/SCK/SCL | bidirectional | Digital I/O (Schmitt Trigger input) that serves as synchronous serial clock input/output for SPI mode (SCK) and I2C mode (SCL). |+| 38 | RD0/PSP0 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 0 (PSP0). |+| 39 | RD1/PSP1 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 1 (PSP1). |+| 40 | RD2/PSP2 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 2 (PSP2). |+| 41 | RD3/PSP3 | bidirectional | Digital I/O (ST/TTL input) that serves as Parallel Slave Port data bit 3 (PSP3). |+| 42 | RC4/SDI/SDA | bidirectional | Digital I/O (Schmitt Trigger input) that serves as SPI data in (SDI) and I2C data I/O (SDA). |+| 43 | RC5/SDO | bidirectional | Digital I/O (Schmitt Trigger input) that serves as SPI data out (SDO). |+| 44 | RC6/TX/CK | bidirectional | Digital I/O (Schmitt Trigger input) that serves as USART asynchronous transmit (TX) and USART synchronous clock (CK). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip Tech |+| Package | TQFP-44(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 44 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Ambient temperature under bias | | -55 | | 125 | °C | | 121 |+| Storage temperature | | -65 | | 150 | °C | | 121 |+| Voltage on VDD with respect to VSS | | -0.3 | | 6.5 | V | | 121 |+| Voltage on MCLR with respect to VSS | | 0 | | 13.5 | V | Note 2 | 121 |+| Voltage on RA4 with respect to VSS | | 0 | | 12 | V | | 121 |+| Total power dissipation | | | | 1 | W | Note 1 | 121 |+| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VDD | 121 |+| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VDD | 121 |+| Operating temperature (industrial) | TA | -40 | | 85 | °C | Standard Operating Conditions, industrial | 123 |+| Supply voltage | VDD | 4 | | 5.5 | V | All configurations | 123 |+| Supply voltage with BOR enabled | VBOR* | | | 5.5 | V | BOR enabled (Note 7) | 123 |+| Brown-out Reset voltage | VBOR | 3.65 | 4 | 4.35 | V | BODEN bit in configuration word enabled | 123 |+| Brown-out Reset current | ΔIBOR | | 25 | 200 | µA | BOR enabled, VDD = 5.0V | 124 |+| Supply current, XT or RC oscillator | IDD | | 0.9 | 4 | mA | XT, RC osc configuration, FOSC = 4 MHz, VDD = 5.5V (Note 4) | 124 |+| Supply current, HS oscillator | IDD | | 5.2 | 15 | mA | HS osc configuration, FOSC = 20 MHz, VDD = 5.5V | 124 |+| Power-down current | IPD | | 5 | 42 | µA | VDD = 4.0V, WDT enabled, -40°C to +85°C | 124 |+| Power-down current | IPD | | 0.1 | 19 | µA | VDD = 4.0V, WDT disabled, -40°C to +85°C | 124 |+| Power-down current | IPD | | 10.5 | 57 | µA | VDD = 4.0V, WDT enabled, -40°C to +125°C | 124 |+| Power-down current | IPD | | 1.5 | 42 | µA | VDD = 4.0V, WDT disabled, -40°C to +125°C | 124 |+| Input low voltage, I/O ports with TTL buffer | VIL | | | 0.8 | V | 4.5V ≤ VDD ≤ 5.5V | 125 |+| Input low voltage, OSC1 (XT and LP mode) | VIL | | | 0.3 | V | OSC1 in XT and LP mode | 125 |+| Input high voltage, I/O ports with TTL buffer | VIH | 2 | | | V | 4.5V ≤ VDD ≤ 5.5V | 125 |+| Input high voltage, OSC1 (XT and LP mode) | VIH | 1.6 | | | V | OSC1 in XT and LP mode | 125 |+| Input leakage current, I/O ports | IIL | -1 | | 1 | µA | Vss ≤ VPIN ≤ VDD, pin at hi-impedance | 125 |+| Input leakage current, MCLR and RA4/T0CKI | IIL | -5 | | 5 | µA | Vss ≤ VPIN ≤ VDD | 125 |+| Input leakage current, OSC1 | IIL | -5 | | 5 | µA | Vss ≤ VPIN ≤ VDD, XT, HS and LP osc configuration | 125 |+| PORTB weak pull-up current | IPURB | 50 | 250 | 400 | µA | VDD = 5V, VPIN = VSS | 125 |+| Output low voltage, I/O ports | VOL | | | 0.6 | V | IOL = 8.5 mA, VDD = 4.5V, -40°C to +125°C | 126 |+| Output low voltage, OSC2/CLKOUT (RC osc) | VOL | | | 0.6 | V | IOL = 1.6 mA, VDD = 4.5V, -40°C to +125°C | 126 |+| Open drain high voltage, RA4 pin | VOD | | | 12 | V | RA4 pin | 126 |+| OSC2 pin capacitive loading | COSC2 | | | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 126 |+| All I/O pins and OSC2 (RC mode) capacitive loading | CIO | | | 50 | pF | | 126 |+| SCL, SDA in I2C mode capacitive loading | CB | | | 400 | pF | | 126 |+| Program FLASH endurance | EP | 100 | 1000 | | E/W | 25°C at 5V | 126 |+| VDD for read | VPR | 2 | | 5.5 | V | | 126 |+| Oscillator frequency, XT osc mode | FOSC | 0.1 | | 4 | MHz | XT osc mode | 128 |+| Oscillator frequency, HS osc mode | FOSC | 4 | | 20 | MHz | HS osc mode | 128 |+| Oscillator frequency, LP osc mode | FOSC | 5 | | 200 | kHz | LP osc mode | 128 |+| External clock input period, XT osc mode | TOSC | 1000 | | | ns | XT osc mode | 128 |+| External clock input period, HS osc mode | TOSC | 50 | | | ns | HS osc mode | 128 |+| External clock input period, LP osc mode | TOSC | 5 | | | ms | LP osc mode | 128 |+| Instruction cycle time | TCY | 200 | | | ns | TCY = 4/FOSC | 128 |+| External clock high or low time, XT oscillator | TosL,TosH | 500 | | | ns | XT oscillator | 128 |+| External clock high or low time, LP oscillator | TosL,TosH | 2.5 | | | ms | LP oscillator | 128 |+| External clock high or low time, HS oscillator | TosL,TosH | 15 | | | ns | HS oscillator | 128 |+| OSC1 (Q1 cycle) to port output valid | TosH2ioV | | 100 | 255 | ns | | 129 |+| OSC1 (Q2 cycle) to port input invalid (I/O hold time) | TosH2ioI | 100 | | | ns | Standard (F) | 129 |+| Port output rise time | TioR | | 10 | 40 | ns | Standard (F) | 129 |+| Port output fall time | TioF | | 10 | 40 | ns | Standard (F) | 129 |+| Reference voltage VREF | VREF | 2.5 | | 5.5 | V | -40°C to +125°C | 140 |+| Recommended impedance of analog voltage source | ZAIN | | | 10 | kΩ | | 140 |+| VREF input current during VAIN acquisition | IREF | -5 | | 5 | µA | During VAIN acquisition | 140 |+| VREF input current during A/D conversion cycle | IREF | | | 500 | µA | During A/D conversion cycle | 140 |+| A/D clock period, TOSC based | TAD | 1.6 | | | µs | TOSC based, VREF ≥ 3.0V | 141 |++## CAD (KiCad official)++- Symbol: `PIC16F77-I`+- Footprint: `Package_QFP:TQFP-44_10x10mm_P0.8mm`+- 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)+- 3D model files: `pic16f77-i-etched.step` / `pic16f77-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic16f77-i.step` / `pic16f77-i.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182464926179328) (174 pp, sha256 `81a107b5141fded6`, retrieved 2026-10-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/pic16f77-i-datasheet.pdf)
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