(version 1)

# PCBWay 4-layer design rules (standard process)
# 
# Min trace width: 0.127 mm (5.0 mil) - outer layers, 1oz (35um) conventional: 5mil (capabilities table, 'min width/spacing of outer layer', archive sha 694ce30266e8)
# Min spacing: 0.1524 mm (6.0 mil) - outer layers, 1oz conventional: 6mil (capabilities table). Inner layers publish 5mil (minSpacingInner), but KiCad cannot set a per-layer clearance floor without a custom clearance rule, which overrides netclass spacing; the board floor therefore uses the outer value, 1mil above the published inner minimum.
# Min drill: 0.2 mm (7.87 mil)
# Min via: 0.2 mm hole / 0.5 mm pad
# Annular ring: via 0.15 mm, pad 0.254 mm
# Copper to board edge: 0.25 mm
# Hole to hole: 0.45 mm
# Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.4 mm
# Copper weight options: 0.5 oz, 1 oz, 1.5 oz, 2 oz, 3 oz, 4 oz
# Surface finishes: HASL with lead, HASL lead free, Immersion gold (ENIG), OSP, Immersion Tin
# Max board size: 508 x 600 mm
# 
# Min board thickness 0.6mm, max board thickness 3.2mm. Min inner layer isolation ring (hole to inner layer conductor, before compensation) 7mil (0.1778mm). Inner layer copper weight options 1oz or 1.5oz. Max aspect ratio 8:1.
# 
# Sources:
# - https://www.pcbway.com/capabilities.html (read 2026-09-03)
# - https://www.pcbway.com/capabilities.html (read 2026-11-02)
# - https://www.pcbway.com/helpcenter/Engineering_Questions/limited_holes_spacing.html (read 2026-11-02)
# - https://www.pcbway.com/pcb_prototype/PCB_Manufacturing_tolerances.html (read 2026-11-02)
# - https://m.pcbway.com/capabilities.html (read 2026-11-02)

(rule "min-track-width-outer"
  (severity error)
  (constraint track_width (min 0.127mm))
  (layer outer))

(rule "min-track-width-inner"
  (severity error)
  (constraint track_width (min 0.1016mm))
  (layer inner))

(rule "min-hole"
  (severity error)
  (constraint hole_size (min 0.2mm)))

(rule "min-via-hole"
  (severity error)
  (constraint hole_size (min 0.2mm))
  (condition "A.Type == 'Via'"))

(rule "min-via-diameter"
  (severity error)
  (constraint via_diameter (min 0.5mm))
  (condition "A.Type == 'Via'"))

(rule "min-via-annular-width"
  (severity error)
  (constraint annular_width (min 0.15mm))
  (condition "A.Type == 'Via'"))

(rule "min-pad-annular-width"
  (severity error)
  (constraint annular_width (min 0.254mm))
  (condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole'"))

(rule "min-edge-clearance"
  (severity error)
  (constraint edge_clearance (min 0.25mm)))

(rule "min-hole-to-hole-via"
  (severity error)
  (constraint hole_to_hole (min 0.3mm)))

(rule "min-hole-to-hole-component"
  (severity error)
  (constraint hole_to_hole (min 0.45mm))
  (condition "A.Type == 'Pad' || B.Type == 'Pad'"))

(rule "min-hole-to-inner-copper"
  (severity error)
  (constraint hole_clearance (min 0.1778mm)))

(rule "min-silk-height"
  (severity error)
  (constraint text_height (min 0.8mm))
  (layer "*.SilkS")
  (condition "A.Type == 'Text' || A.Type == 'Text Box'"))

(rule "min-silk-thickness"
  (severity error)
  (constraint text_thickness (min 0.15mm))
  (layer "*.SilkS")
  (condition "A.Type == 'Text' || A.Type == 'Text Box'"))