NUC505DS13Y

@@ -0,0 +1,111 @@+# NUC505DS13Y++**Nuvoton Tech** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(7x7)++NUC505DS13Y from Nuvoton Tech, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | nRESET | input | External reset input, active LOW, with internal pull-up. Drive low to reset the device to initial state. |+| 2 | PD.0/ICE_CLK/I2C0_SCL | bidirectional | Multi-function pin. MFP0: ICE_CLK serial-wired debugger clock (default in ICE mode). MFP0: PD.0 GPIO. MFP2: I2C0_SCL clock. |+| 3 | PD.1/ICE_DAT/I2C0_SDA | bidirectional | Multi-function pin. MFP0: ICE_DAT serial-wired debugger data (default in ICE mode). MFP0: PD.1 GPIO. MFP2: I2C0_SDA data. |+| 4 | PB.13/SPI1_MISO/USBH1_D-/UART2_nRTS/PWM_CH3 | bidirectional | GPIO PB.13. Alt: SPI1_MISO, USB host-lite 1 D-, UART2 nRTS, PWM channel 3. |+| 5 | PB.14/USBH1_D+/I2C1_SCL | bidirectional | GPIO PB.14. Alt: USB host-lite 1 D+, I2C1_SCL clock. |+| 6 | PB.15/USBH1_D-/I2C1_SDA | bidirectional | GPIO PB.15. Alt: USB host-lite 1 D-, I2C1_SDA data. |+| 7 | PC.0/SD_CMD | bidirectional | GPIO PC.0. Alt: SD/SDH mode command/response line. |+| 8 | VDD | power_in | Power supply for I/O ports, DC 3.3 V. |+| 9 | VSS | power_in | Ground. |+| 10 | XT1_IN | input | External 12 MHz (high-speed) crystal input pin. |+| 11 | XT1_OUT | output | External 12 MHz (high-speed) crystal output pin. |+| 12 | VDD12 | power_in | Digital core power supply, DC 1.2 V. |+| 13 | USB_D- | bidirectional | USB 2.0 HS device differential signal D-. |+| 14 | USB_D+ | bidirectional | USB 2.0 HS device differential signal D+. |+| 15 | AVDDUSB | power_in | Analog power supply for USB PHY, DC 3.3 V. |+| 16 | USB_REXT | passive | USB reference resistor pin; connect a 12.1 kΩ resistor to ground for USB PHY biasing. |+| 17 | VBAT | power_in | Battery backup supply for RTC, DC 3.3 V. |+| 18 | RTC_RPWR | output | Active-high enable output for external power control source (RTC-controlled power switch). |+| 19 | RTC_nRWAKE | input | Active-low system power enable trigger from RTC wake source. |+| 20 | PA.8/SPIM_SS/I2S_LRCLK/UART1_TXD | bidirectional | GPIO PA.8. Alt: SPIM slave-select, I2S LRCLK, UART1 TXD. |+| 21 | PA.9/SPIM_CLK/I2S_BCLK/UART1_RXD/SYSCFG[0] | bidirectional | GPIO PA.9. Alt: SPIM serial clock, I2S bit clock, UART1 RXD. Also sampled at reset as SYSCFG[0] system configuration bit. |+| 22 | PA.10/SPIM_MOSI/I2C1_SCL/SD_CLK/SYSCFG[1] | bidirectional | GPIO PA.10. Alt: SPIM MOSI (also QSPI D0), I2C1_SCL, SD_CLK. Also sampled at reset as SYSCFG[1]. |+| 23 | PA.11/SPIM_MISO/I2C1_SDA/SD_CMD | bidirectional | GPIO PA.11. Alt: SPIM MISO (also QSPI D1), I2C1_SDA, SD command line. |+| 24 | PA.12/SPIM_D2/TM0_CNT_OUT | bidirectional | GPIO PA.12. Alt: SPIM/QSPI data 2, Timer0 event counter input / toggle output. |+| 25 | PA.13/SPIM_D3/TM0_EXT/SD_nCD | bidirectional | GPIO PA.13. Alt: SPIM/QSPI data 3, Timer0 external capture input, SD card-detect. |+| 26 | PA.14/I2C0_SCL/SD_DAT0 | bidirectional | GPIO PA.14. Alt: I2C0_SCL, SD data line 0. |+| 27 | PA.15/I2C0_SDA/SD_DAT1 | bidirectional | GPIO PA.15. Alt: I2C0_SDA, SD data line 1. |+| 28 | VDD | power_in | Power supply for I/O ports, DC 3.3 V. |+| 29 | PB.0/I2C0_SCL/UART0_TXD/SD_DAT2 | bidirectional | GPIO PB.0. Alt: I2C0_SCL, UART0 TXD, SD data line 2. |+| 30 | PB.1/I2C0_SDA/UART0_RXD/SD_DAT3 | bidirectional | GPIO PB.1. Alt: I2C0_SDA, UART0 RXD, SD data line 3. |+| 31 | PB.2/SPI0_SS/SD_CMD | bidirectional | GPIO PB.2. Alt: SPI0 slave-select, SD command line. |+| 32 | PB.3/SPI0_CLK/SD_CLK/SYSCFG[2] | bidirectional | GPIO PB.3. Alt: SPI0 serial clock, SD clock. Also sampled at reset as SYSCFG[2]. |+| 33 | PB.4/SPI0_MOSI/SYSCFG[3] | bidirectional | GPIO PB.4. Alt: SPI0 MOSI. Also sampled at reset as SYSCFG[3]. |+| 34 | PB.5/SPI0_MISO/SD_nCD | bidirectional | GPIO PB.5. Alt: SPI0 MISO, SD card-detect. |+| 35 | PB.6/UART1_TXD/SD_DAT0 | bidirectional | GPIO PB.6. Alt: UART1 TXD, SD data line 0. |+| 36 | PB.7/UART1_RXD/SD_DAT1 | bidirectional | GPIO PB.7. Alt: UART1 RXD, SD data line 1. |+| 37 | USB_VBUS33 | input | USB VBUS-detect input (3.3 V level); indicates presence of USB bus power. |+| 38 | PB.8/USBH_PWEN/TM1_CNT_OUT/UART1_nCTS/SD_DAT2 | bidirectional | GPIO PB.8. Alt: USB host external power enable, Timer1 event counter I/O, UART1 nCTS, SD data line 2. |+| 39 | PB.9/USBH_OVD/TM1_EXT/UART1_nRTS/SD_DAT3 | bidirectional | GPIO PB.9. Alt: USB host bus over-voltage detect, Timer1 external capture, UART1 nRTS, SD data line 3. |+| 40 | VSS | power_in | Ground. |+| 41 | AVDDHP | power_in | Analog power supply for CODEC headphone driver, DC 3.3 V. |+| 42 | LHPOUT | output | Headphone left-channel analog output from internal 24-bit CODEC. |+| 43 | RHPOUT | output | Headphone right-channel analog output from internal 24-bit CODEC. |+| 44 | AVSSHP | power_in | Analog ground for CODEC headphone driver. |+| 45 | VMID | passive | Headphone reference (mid-rail) power. Requires external decoupling capacitor to ground. |+| 46 | AVDDCODEC | power_in | Analog power supply for internal CODEC, DC 3.3 V. |+| 47 | AVDDADC | power_in | Analog power supply for the SAR ADC, DC 3.3 V. |+| 48 | AVSSADC | power_in | Analog ground for the SAR ADC. |+| 49 | PA.0/ADC_CH0 | bidirectional | GPIO PA.0. Alt: 12-bit ADC channel 0 analog input. |+| 50 | PA.1/ADC_CH1 | bidirectional | GPIO PA.1. Alt: 12-bit ADC channel 1 analog input. |+| 51 | PA.2/ADC_CH2/I2S_MCLK | bidirectional | GPIO PA.2. Alt: 12-bit ADC channel 2 analog input, I2S master clock output. |+| 52 | PA.3/ADC_CH3/I2S_DI | bidirectional | GPIO PA.3. Alt: 12-bit ADC channel 3 analog input, I2S data input. |+| 53 | PA.4/ADC_CH4/I2S_DO | bidirectional | GPIO PA.4. Alt: 12-bit ADC channel 4 analog input, I2S data output. |+| 54 | PA.5/ADC_CH5 | bidirectional | GPIO PA.5. Alt: 12-bit ADC channel 5 analog input. |+| 55 | PA.6/ADC_CH6 | bidirectional | GPIO PA.6. Alt: 12-bit ADC channel 6 analog input. |+| 56 | PA.7/ADC_CH7 | bidirectional | GPIO PA.7. Alt: 12-bit ADC channel 7 analog input. |+| 57 | VDD12 | power_in | Digital core power supply, DC 1.2 V. |+| 58 | PB.10/SPI1_SS/I2C1_SCL/UART2_TXD/PWM_CH0 | bidirectional | GPIO PB.10. Alt: SPI1 slave-select, I2C1_SCL, UART2 TXD, PWM channel 0. |+| 59 | PB.11/SPI1_CLK/I2C1_SDA/UART2_RXD/PWM_CH1 | bidirectional | GPIO PB.11. Alt: SPI1 serial clock, I2C1_SDA, UART2 RXD, PWM channel 1. |+| 60 | PB.12/SPI1_MOSI/USBH1_D+/UART2_nCTS/PWM_CH2 | bidirectional | GPIO PB.12. Alt: SPI1 MOSI, USB host-lite 1 D+, UART2 nCTS, PWM channel 2. |+| 61 | VDD | power_in | Power supply for I/O ports, DC 3.3 V. |+| 62 | VDD | power_in | Main 3.3 V power supply. |+| 63 | LDO_CAP | passive | Internal 1.2 V LDO output pin. Requires an external decoupling capacitor to VSS. |+| 64 | VSS | power_in | Ground. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nuvoton Tech |+| Package | LQFP-64(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 64 |++## Ordering variants++Same part, different packaging or reel option.++- `NUC505DS13Y`+- `NUC505DS13YDSA`+- `NUC505DS13YDLA`+- `NUC505DS13YDL13Y`+- `NUC505DS13YYLA`+- `NUC505DS13YYLA2Y`+- `NUC505DS13YYO13Y`++## CAD (KiCad official)++- Symbol: `NUC505DS13Y`+- Footprint: `Package_QFP:LQFP-64_7x7mm_P0.4mm`+- 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nuvoton Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589042079775670272) (None pp, sha256 `27cb8319f351ab4c`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/nuc505ds13y-datasheet.pdf)