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Set visibility: public

Ray ·735ac9c9dd ·1mo ago ·parent 25a1980
1 file changed +8−5
page.json+8−5
@@ -32,7 +32,7 @@         "number": "1",         "name": "VIN",         "type": "power_in",-        "description": "Power input. Accepts 6V to 60V supply (absolute max 65V). Bypass locally to GND with a bulk (e.g. 47\u00b5F) and a ceramic (e.g. 1\u00b5F) capacitor."+        "description": "Power input. Accepts 6V to 60V supply (absolute max 65V). Bypass locally to GND with a bulk (e.g. 47µF) and a ceramic (e.g. 1µF) capacitor."       },       {         "number": "2",@@ -44,7 +44,7 @@         "number": "3",         "name": "EN/DIM",         "type": "input",-        "description": "Enable and PWM/analog dimming input. Below ~0.3V the part is shut down; enable threshold ~0.3V (typ) with ~30 mV hysteresis. Supports PWM dimming from 0.1 kHz to 20 kHz; internal 1.5\u00b5A pull-up to 5V and 25\u00b5A pull-down to GND."+        "description": "Enable and PWM/analog dimming input. Below ~0.3V the part is shut down; enable threshold ~0.3V (typ) with ~30 mV hysteresis. Supports PWM dimming from 0.1 kHz to 20 kHz; internal 1.5µA pull-up to 5V and 25µA pull-down to GND."       },       {         "number": "4",@@ -56,13 +56,13 @@         "number": "5",         "name": "DRV",         "type": "output",-        "description": "External NMOS gate driver output. High level ~5.5V (VCC), source resistance ~1.4\u03a9, sink resistance ~0.5\u03a9. Minimum ON time 120 ns, minimum OFF time 130 ns, maximum switching frequency 1 MHz."+        "description": "External NMOS gate driver output. High level ~5.5V (VCC), source resistance ~1.4Ω, sink resistance ~0.5Ω. Minimum ON time 120 ns, minimum OFF time 130 ns, maximum switching frequency 1 MHz."       },       {         "number": "6",         "name": "VCC",         "type": "power_out",-        "description": "Internal LDO output / gate-drive rail. Typically 6V (5.5V min) with UVLO rising threshold ~5.7V and ~1.1V hysteresis. Bypass to GND with a ceramic capacitor (e.g. 2.2\u00b5F); do not load externally."+        "description": "Internal LDO output / gate-drive rail. Typically 6V (5.5V min) with UVLO rising threshold ~5.7V and ~1.1V hysteresis. Bypass to GND with a ceramic capacitor (e.g. 2.2µF); do not load externally."       }     ],     "provenance": {@@ -126,5 +126,8 @@     "docs/ndp36501se-r-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file