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Initial commit: component/ncv59745amw1015tag

Ray ·669bc07464 ·1mo ago
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README.mdadded+65
@@ -0,0 +1,65 @@+# NCV59745AMW1015TAG++**onsemi** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(4x4)++NCV59745AMW1015TAG from onsemi, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT | power_out | Regulated output voltage pin. Tied together with pins 19 and 20. Requires a ceramic output capacitor >= 10 uF effective value; output current in excess of 3.0 A; VOUT range 0.8 V to 3.6 V (fixed 1.015 V for the AMW1015TAG suffix). |+| 2 | SNS | input | Output voltage sense input pin. Used by the internal error amplifier to regulate VOUT. Must not be left floating; connect at/near the load-side of OUT for Kelvin sensing. |+| 3 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 4 | PG | output | Power-Good open-drain, active-high output. High-impedance when VOUT exceeds the PG trip threshold (~91% of VOUT typ), low-impedance below it. Requires a 10 kOhm to 100 kOhm external pull-up to a rail up to 5.5 V; may be left floating if unused. PG sink current 0 to 1.5 mA; VPG,LO <= 0.3 V at 1 mA. |+| 5 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 6 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 7 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 8 | GND | power_in | Device ground. Must be connected to the PCB ground plane along with pin 18 and the exposed thermal pad. |+| 9 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 10 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 11 | NC | unconnected | No connection. True NC pin - may be left floating or tied to GND for improved thermal contact to the PCB top-side plane. |+| 12 | BIAS | power_in | Bias input voltage powering the error amplifier, VREF reference, and internal control circuitry. VBIAS range 2.2 V to 5.5 V; recommended CBIAS >= 1 uF ceramic connected directly at the pin. Absolute max -0.3 V to +6 V. |+| 13 | SS | passive | Soft-Start programming pin. External capacitor CSS to GND sets the soft-start ramp time per tSS[ms] = CSS[nF] x 0.13 (max recommended CSS = 1 uF). Charged by ISS ~ 6.2 x VOUT(NOM)/0.8V uA. Absolute max -0.3 V to (VBIAS+0.3) V, <= 6 V. |+| 14 | EN | input | Enable input. Drive high (VEN,HI >= 1.1 V) to enable the regulator; drive low (VEN,LO <= 0.4 V) for shutdown. Must not be left floating; features 100 mV hysteresis and 20 us deglitch. IEN ~ 0.3 uA @ VEN = 5 V. Absolute max -0.3 V to +6 V. |+| 15 | IN | power_in | Unregulated input voltage to the pass device. Pins 15, 16, 17 must be tied together. VIN range 0.8 V to 5.5 V (VIN >= VOUT + VDO); recommended CIN >= 4.7 uF ceramic connected directly at the pin. Absolute max -0.3 V to +6 V. |+| 16 | IN | power_in | Unregulated input voltage to the pass device. Tied together with pins 15 and 17. |+| 17 | IN | power_in | Unregulated input voltage to the pass device. Tied together with pins 15 and 16. |+| 18 | GND | power_in | Device ground. Must be connected to the PCB ground plane along with pin 8 and the exposed thermal pad. |+| 19 | OUT | power_out | Regulated output voltage pin. Tied together with pins 1 and 20. |+| 20 | OUT | power_out | Regulated output voltage pin. Tied together with pins 1 and 19. |+| 21 | PAD | power_in | Exposed thermal pad on the bottom of the QFNW20 package. Must be soldered to the PCB ground plane for increased thermal performance (RthetaJA = 40 C/W with recommended thermal-via array). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | QFN-20(4x4) |+| Category | Power Management (PMIC) |+| Pins | 21 |++## Ordering variants++Same part, different packaging or reel option.++- `NCV59745AMW100TAG`+- `NCV59745AMW1015TAG`+- `NCV59745AMW180TAG`+- `NCV59745AMW1015TAGAMW250TAG`++## CAD (KiCad official)++- Symbol: `NCV59745AMW1015TAG`+- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`+- 3D model: QFN-20(4x4) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929233371975680) (12 pp, sha256 `04b620a2c3bcc9d9`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncv59745amw1015tag-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "ncv59745amw1015tag",+  "version": "0.1.0",+  "type": "component",+  "description": "onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "ncv59745amw1015tag"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ncv59745amw1015tag.kicad_sym",+    "ncv59745amw1015tag.kicad_mod",+    "ncv59745amw1015tag.glb",+    "ncv59745amw1015tag.step",+    "ncv59745amw1015tag.lbr",+    "docs/hero.png",+    "docs/ncv59745amw1015tag-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file