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NCP5181DR2G
Public Made by Adomby adom
onsemi Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+80docs/hero.pngdocs/ncp5181dr2g-datasheet.pdf+4833ncp5181dr2g-etched.glbncp5181dr2g-hero.glbncp5181dr2g-hero.overlay.json+260ncp5181dr2g.glbncp5181dr2g.kicad_mod+300ncp5181dr2g.kicad_sym+45ncp5181dr2g.lbr+130ncp5181dr2g.step+3030package.json+196page.json+202viewers/footprint.html+1viewers/symbol.html+1README.mdadded+80@@ -0,0 +1,80 @@+# NCP5181DR2G++**onsemi** · Gate Drivers · SOIC-8++NCP5181DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN_HI | input | Logic input for the high-side driver, output in phase with the input; compatible with 3.3 V and 5 V logic, accepts up to VCC swing, with VIL max 0.8 V and VIH min 2.3 V. |+| 2 | IN_LO | input | Logic input for the low-side driver, output in phase with the input; compatible with 3.3 V and 5 V logic, accepts up to VCC swing, with VIL max 0.8 V and VIH min 2.3 V. |+| 3 | GND | power_in | Ground reference for the device. |+| 4 | DRV_LO | output | Low-side gate drive output, rated for 1.4 A source and 2.2 A sink pulsed short-circuit current and driven between -0.3 V and VCC+0.3 V. |+| 5 | VCC | power_in | Low-side and main power supply, absolute maximum -0.3 V to 20 V, with gate drive supply range 10 V to 20 V. |+| 6 | BRIDGE | power_in | Bootstrap return or high-side floating supply return, rated -1 V to 600 V, with VBOOT-VBRIDGE limited to 0 V to 20 V. |+| 7 | DRV_HI | output | High-side gate drive output, limited to VBRIDGE-0.3 V to VBOOT+0.3 V. |+| 8 | VBOOT | power_in | Bootstrap power supply for the high-side driver, rated -1 V to 620 V, with VBOOT-VBRIDGE limited to 0 V to 20 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-8 |+| Category | Motor Driver ICs |+| Pins | 8 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Output Resistor Source (Typical Value @ 25°C Only) | ROH | | 5 | 12 | | Typical Value @ 25°C Only | 4 |+| Output Resistor Sink (Typical Value @ 25°C Only) | ROL | | 2 | 8 | | Typical Value @ 25°C Only | 4 |+| Turn-on Propagation Delay | tON | | 100 | 170 | ns | Vbridge = 0 V | 4 |+| Turn-off Propagation Delay | tOFF | | 100 | 170 | ns | Vbridge = 0 V or 50 V (Note 2) | 4 |+| Output Voltage Risetime | tr | | 40 | 60 | ns | from 10% to 90% @ VCC = 15 V with 1 nF Load | 4 |+| Output Voltage Falling Edge | tf | | 20 | 40 | ns | from 90% to 10% @ VCC = 15 V with 1 nF Load | 4 |+| Propagation Delay Matching between the High Side and the Low Side | t | | 20 | 35 | ns | @ 25°C (Note 3) | 4 |+| Minimum Input Pulse Width that Changes the Output | tPW | | | 100 | ns | | 4 |+| Low Level Input Voltage Threshold | VIN | | | 0.8 | V | | 4 |+| High Level Input Voltage Threshold | VIN | 2.3 | | | V | | 4 |+| VCC UV Startup Voltage Threshold | VCC_stup | 7.9 | 8.9 | 9.8 | V | | 4 |+| VCC UV Shutdown Voltage Threshold | VCC_shtdwn | 7.3 | 8.2 | 9 | V | | 4 |+| Hysteresis on VCC | VCC_hyst | 0.3 | 0.7 | | V | | 4 |+| Vboot Startup Voltage Threshold Reference to Bridge Pin | Vboot_stup | 7.9 | 8.9 | 9.8 | V | Reference to Bridge Pin (Vboot_stup = Vboot − Vbridge) | 4 |+| Vboot UV Shutdown Voltage Threshold | Vboot_shtdwn | 7.3 | 8.2 | 9 | V | | 4 |+| Hysteresis on Vboot | Vboot_shtdwn | 0.3 | 0.7 | | V | | 4 |+| Leakage Current on High Voltage Pins to GND | IHV_LEAK | | 0.5 | 40 | A | VBOOT = VBRIDGE = DRV_HI = 600 V | 4 |+| Consumption in Active Mode | ICC1 | | 4.5 | 6.5 | mA | VCC = Vboot, fsw = 100 kHz and 1 nF Load on Both Driver Outputs | 4 |+| Consumption in Inhibition Mode | ICC2 | | 250 | 400 | A | VCC = Vboot | 4 |+| Main Power Supply Voltage | VCC | -0.3 | | 20 | V | | 3 |+| High Voltage BOOT Pin | VBOOT | -1 | | 620 | V | | 3 |+| High Voltage BRIDGE Pin | VBRIDGE | -1 | | 600 | V | | 3 |+| VHV: Floating Supply Voltage | VBOOT − VBRIDGE | 0 | | 20 | V | | 3 |+| Allowable Output Slew Rate | dVBRIDGE/dt | | | 50 | V/ns | | 3 |+| Inputs IN_HI, IN_LO | VIN_XX | -1 | | | V | Upper limit printed as VCC+0.3 V (not numeric) | 3 |+| SO-8 Thermal Resistance, Junction-to-Air | RJA | | 178 | | °C/W | SO-8 package | 3 |+| Maximum Operating Junction Temperature | TJ_max | | | 150 | °C | | 3 |+| Gate Drive Supply Range | VCC | 10 | | 20 | V | Gate drive supply range as stated in Features | 1 |+| Operating Ambient Temperature | TA | -40 | | 125 | °C | Electrical characteristics range (−40°C < TA < 125°C) | 4 |++## CAD (KiCad official)++- Symbol: `NCP5181DR2G`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `ncp5181dr2g-etched.step` / `ncp5181dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp5181dr2g.step` / `ncp5181dr2g.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp5181-d.pdf) (14 pp, sha256 `bf78f6c4fa9021a8`, retrieved 2026-10-19, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncp5181dr2g-datasheet.pdf)
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