component
NCP4305DMTTWG
Public Made by Adomby adom
onsemi AC-DC Controllers & Regulators, WDFN-8(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+116@@ -0,0 +1,116 @@+# NCP4305DMTTWG++**onsemi** · AC-DC Controllers & Regulators · WDFN-8(2x2)++NCP4305DMTTWG from onsemi, in a WDFN-8(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCC | power_in | Supply voltage pin, absolute maximum -0.3 to 37.0 V, with UVLO of 4.5 V for the D version. |+| 2 | MIN_TOFF | passive | Adjusts the minimum off time period by connecting a resistor to ground. |+| 3 | MIN_TON | passive | Adjusts the minimum on time period by connecting a resistor to ground. |+| 4 | LLD | input | Modulates the driver clamp level and/or turns the driver off during light load conditions. |+| 5 | TRIG/DIS | input | Ultrafast turn-off input (7.5 ns) to turn off the SR MOSFET in CCM applications, and it activates disable mode if pulled up for more than 100 µs. |+| 6 | CS | input | Current sense pin that detects current through the SR MOSFET and/or its body diode, with a 0 mV basic turn-off threshold, a -4 to 200 V rating, and a series resistor that can lower the threshold. |+| 7 | GND | power_in | Ground for the SR MOSFET driver, VCC decoupling capacitor, min on/off time resistors, LLD and trigger inputs, wired directly to the SR MOSFET source by Kelvin connection. |+| 8 | DRV | output | Driver output for the SR MOSFET, with a 9.5 V clamp for the D version and a -0.3 to 17.0 V absolute maximum rating. |+| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | WDFN-8(2x2) |+| Category | Power Supply Chip |+| Pins | 9 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| VCC UVLO rising | VCCON | 4.2 | 4.45 | 4.8 | V | VCC rising (ver. A, D & Q) | 6 |+| VCC UVLO falling | VCCOFF | 3.7 | 3.95 | 4.2 | V | VCC falling (ver. A, D & Q) | 6 |+| Current consumption, CLOAD=0 nF, WDFN | ICC | 3.5 | 4.5 | 6 | mA | CLOAD = 0 nF, fSW = 500 kHz, WDFN, B, D, Q | 6 |+| Current consumption, CLOAD=1 nF | ICC | 7.7 | 9 | 10.7 | mA | CLOAD = 1 nF, fSW = 500 kHz, B, D, Q | 6 |+| Current consumption, CLOAD=10 nF | ICC | 40 | 50 | 60 | mA | CLOAD = 10 nF, fSW = 500 kHz, B, D, Q | 6 |+| Current consumption, no switching | ICC | 1.5 | 2 | 2.5 | mA | No switching, VCS = 0 V, RMIN_TON = RMIN_TOFF = 0 k | 6 |+| Maximum driver output voltage | VDRVMAX | 9 | 9.5 | 10.5 | V | VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V, (ver. B, D and Q) | 6 |+| Minimum driver output voltage | VDRVMIN | 3.6 | 4 | 4.4 | V | VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. A, D, Q) | 6 |+| Minimum driver output voltage, LLD | VDRVLLDMIN | 0 | 0.4 | 1.2 | V | VLLD = VCC − VLLDREC V | 6 |+| CS bias current | ICS | -105 | -100 | -95 | µA | VCS = −20 mV | 7 |+| Turn on CS threshold voltage | VTH_CS_ON | -120 | -75 | -40 | mV | | 7 |+| Turn off timer reset threshold voltage | VTH_CS_RESET | 0.42 | 0.48 | 0.54 | V | | 7 |+| Trigger threshold voltage | VTRIG_TH | 1.87 | 2.02 | 2.18 | V | | 7 |+| Trigger blank time after DRV turn-on | tTRIG_BLANK | 35 | 50 | 65 | ns | VCS drops below VTH_CS_ON | 7 |+| Delay to disable mode | tDIS_TIM | 75 | 100 | 125 | µs | VTRIG = 5 V | 7 |+| Disable recovery timer | tDIS_REC | 5 | 8 | 13 | µs | VTRIG goes down from 5 to 0 V | 7 |+| Trigger pull down current | ITRIG | 9 | 13 | 16 | µA | VTRIG = 5 V | 7 |+| Minimum tON time, RMIN_TON=0 | tON_MIN | 35 | 55 | 75 | ns | RMIN_TON = 0 Ω | 7 |+| Minimum tOFF time, RMIN_TOFF=0 | tOFF_MIN | 190 | 245 | 290 | ns | RMIN_TOFF = 0 Ω | 7 |+| Minimum tON time, 10 k | tON_MIN | 0.92 | 1 | 1.08 | µs | RMIN_TON = 10 k | 7 |+| Minimum tOFF time, 10 k | tOFF_MIN | 0.92 | 1 | 1.08 | µs | RMIN_TOFF = 10 k | 7 |+| Minimum tON time, 50 k | tON_MIN | 4.62 | 5 | 5.38 | µs | RMIN_TON = 50 k | 7 |+| Minimum tOFF time, 50 k | tOFF_MIN | 4.62 | 5 | 5.38 | µs | RMIN_TOFF = 50 k | 7 |+| LLD disable threshold | VLLD_DIS | 0.8 | 0.9 | 1 | V | VLLD_DIS = VCC − VLLD | 7 |+| LLD recovery threshold | VLLD_REC | 0.9 | 1 | 1.1 | V | VLLD_REC = VCC − VLLD | 7 |+| LLD disable recovery time | tLLD_DIS_REC | 7 | 12.5 | 16 | µs | | 7 |+| LLD low pass filter frequency | fLPLLD | 6 | 10 | 13 | kHz | | 7 |+| Current consumption in disable mode | ICC_DIS | 40 | 55 | 70 | µA | VLLD = VCC − 0.1 V, VCS = 0 V | 6 |+| Current consumption in disable mode (TRIG) | ICC_DIS | 45 | 65 | 80 | µA | VTRIG = 5 V, VLLD = VCC, 3 V, VCS = 0 V | 6 |+| Start-up delay | tSTART_DEL | | 75 | 125 | µs | VCC rising from 0 to VCCON + 1 V @ tr = 10 µs | 6 |+| Current consumption below UVLO | ICC_UVLO | | 75 | 125 | µA | No switching, VCC = VCCOFF, 0.1 V, VCS = 0 V | 6 |+| Output voltage rise-time | tr | | 40 | 55 | ns | CLOAD = 10 nF, 10% to 90% VDRVMAX | 6 |+| Output voltage fall-time | tf | | 20 | 35 | ns | CLOAD = 10 nF, 90% to 10% VDRVMAX | 6 |+| Propagation delay CS to DRV on | tPD_ON | | 35 | 60 | ns | VCS goes down from 4 to −1 V, tf_CS = 5 ns | 7 |+| Propagation delay CS to DRV off | tPD_OFF | | 12 | 23 | ns | VCS goes up from −1 to 4 V, tr_CS = 5 ns | 7 |+| Trigger to DRV propagation delay | tPD_TRIG | | 7.5 | 12.5 | ns | VTRIG goes from 0 to 5 V, tr_TRIG = 5 ns | 7 |+| Turn off CS threshold voltage | VTH_CS_OFF | -1 | | 0 | mV | Guaranteed by Design | 7 |+| CS leakage current | ICS_LEAKAGE | | 0.4 | | µA | VCS = 200 V | 7 |+| Driver source resistance | RDRV_SOURCE | | 1.2 | | Ω | | 6 |+| Driver sink resistance | RDRV_SINK | | 0.5 | | Ω | | 6 |+| Output peak source current | IDRV_SOURCE | | 4 | | A | | 6 |+| Output peak sink current | IDRV_SINK | | 8 | | A | | 6 |+| VCC UVLO hysteresis | VCCHYS | | 0.5 | | V | ver. A, D & Q | 6 |+| Minimum trigger pulse duration | tTRIG_PW_MIN | | 10 | | ns | VTRIG = 5 V; Shorter pulses may not be proceeded | 7 |+| Minimum pulse duration to disable mode end | tDIS_END_MIN | | 200 | | ns | VTRIG = 0 V; Shorter pulses may not be proceeded | 7 |+| LLD disable hysteresis | VLLD_DISH | | 0.1 | | V | | 7 |+| LLD disable time hysteresis | tLLD_DISH | | 45 | | µs | Disable to Normal, Normal to Disable | 7 |+| Driver voltage clamp threshold | VLLDMAX | | 2 | | V | VDRV = VDRVMAX, VLLDMAX = VCC − VLLD | 7 |+| Supply voltage | VCC | -0.3 | | 37 | V | | 5 |+| TRIG/DIS, MIN_TON, MIN_TOFF, MAX_TON, LLD input voltage | VTRIG/DIS, VMIN_TON, VMIN_TOFF, VMAX_TON, VLLD | -0.3 | | | V | max = VCC | 5 |+| Driver output voltage | VDRV | -0.3 | | 17 | V | | 5 |+| Current sense input voltage | VCS | -4 | | 200 | V | | 5 |+| Current sense dynamic input voltage | VCS_DYN | -10 | | 200 | V | tPW = 200 ns | 5 |+| MIN_TON, MIN_TOFF, MAX_TON, LLD, TRIG input current | IMIN_TON, IMIN_TOFF, IMAX_TON, ILLD, ITRIG | -10 | | 10 | mA | | 5 |+| Maximum junction temperature | TJMAX | | | 150 | °C | | 5 |+| Storage temperature | TSTG | -60 | | 150 | °C | | 5 |+| ESD HBM, except pin 6 | ESDHBM | | | 2000 | V | per JESD22-A114E | 5 |+| ESD HBM, pin 6 | ESDHBM | | | 1000 | V | per JESD22-A114E | 5 |+| ESD machine model | ESDMM | | | 200 | V | per JESD22-A115-A | 5 |+| ESD CDM, except pin 6 | ESDCDM | | | 750 | V | per JESD22-C101F | 5 |+| ESD CDM, pin 6 | ESDCDM | | | 250 | V | per JESD22-C101F | 5 |+| Junction to air thermal resistance, WDFN8 | RθJ-A_WDFN8 | | 160 | | °C/W | 1 oz 1 in2 Copper Area | 5 |+| Maximum operating input voltage | VCC | | | 35 | V | | 6 |+| Operating junction temperature | TJ | -40 | | 125 | °C | | 6 |++## CAD (KiCad official)++- Symbol: `NCP4305DMTTWG`+- Footprint: `Package_DFN_QFN:WDFN-8-1EP_2x2mm_P0.5mm_EP0.8x1.2mm`+- 3D model: WDFN-8(2x2), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `ncp4305dmttwg-etched.step` / `ncp4305dmttwg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp4305dmttwg.step` / `ncp4305dmttwg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp4305dmttw-d.pdf) (54 pp, sha256 `a2a29f1aa19397a5`, retrieved 2026-10-27, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncp4305dmttwg-datasheet.pdf)
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Thanks to its high performance drivers and versatility, it can be used in various topologies such as DCM or CCM flyback, quasi resonant flyback, forward and half bridge resonant LLC.)+/Title (NCP4305 - Secondary Side Synchronous Rectifiation Driver for High Efficiency SMPS Topologies)+>>+endobj+2 0 obj+<<+/Type /Pages+/Kids [7 0 R 8 0 R 9 0 R 10 0 R 11 0 R 12 0 R 13 0 R 14 0 R 15 0 R 16 0 R+17 0 R 18 0 R 19 0 R 20 0 R 21 0 R 22 0 R 23 0 R 24 0 R 25 0 R 26 0 R+27 0 R 28 0 R 29 0 R 30 0 R 31 0 R 32 0 R 33 0 R 34 0 R 35 0 R 36 0 R+37 0 R 38 0 R 39 0 R 40 0 R 41 0 R 42 0 R 43 0 R 44 0 R 45 0 R 46 0 R+47 0 R 48 0 R 49 0 R 50 0 R 51 0 R 52 0 R 53 0 R 54 0 R 55 0 R 56 0 R+57 0 R 58 0 R 59 0 R 60 0 R]+/Count 54+>>+endobj+3 0 obj+<<+/DA (/Helv 0 Tf 0 g )+/DR 61 0 R+/Fields []+>>+endobj+4 0 obj+<<+/Length 4147+/Subtype /XML+/Type /Metadata+>>+stream +<?xpacket begin="" id="W5M0MpCehiHzreSzNTczkc9d"?>+<x:xmpmeta xmlns:x="adobe:ns:meta/" x:xmptk="Adobe XMP Core 5.6-c017 91.164464, 2020/06/15-10:20:05 ">+ <rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">+ <rdf:Description rdf:about=""+ xmlns:xmp="http://ns.adobe.com/xap/1.0/"+ xmlns:pdf="http://ns.adobe.com/pdf/1.3/"+ xmlns:dc="http://purl.org/dc/elements/1.1/"+ xmlns:xmpMM="http://ns.adobe.com/xap/1.0/mm/"+ xmlns:illustrator="http://ns.adobe.com/illustrator/1.0/">+ <xmp:CreateDate>2016-06-21T07:45:11-07:00</xmp:CreateDate>+ <xmp:CreatorTool>BroadVision, Inc.</xmp:CreatorTool>+ <xmp:ModifyDate>2020-08-24T09:15:33+02:00</xmp:ModifyDate>+ <xmp:MetadataDate>2020-08-24T09:15:33+02:00</xmp:MetadataDate>+ <pdf:Producer>Acrobat Distiller 10.0.0 (Windows)</pdf:Producer>+ <dc:format>application/pdf</dc:format>+ <dc:title>+ <rdf:Alt>+ <rdf:li xml:lang="x-default">NCP4305 - Secondary Side Synchronous Rectifiation Driver for High Efficiency SMPS Topologies</rdf:li>+ </rdf:Alt>+ </dc:title>+ <dc:creator>+ <rdf:Seq>+ <rdf:li>ON Semiconductor</rdf:li>+ </rdf:Seq>+ </dc:creator>+ <dc:description>+ <rdf:Alt>+ <rdf:li xml:lang="x-default">The NCP4305 is high performance driver tailored to control a synchronous rectification MOSFET in switch mode power supplies. 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