component
NCP1566MNTXG
Public Made by Adomby adom
onsemi AC-DC Controllers And Regulators, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+128@@ -0,0 +1,128 @@+# NCP1566MNTXG++**onsemi** · AC-DC Controllers And Regulators · QFN-24-EP(4x4)++NCP1566MNTXG from onsemi, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RAMP | passive | PWM modulator ramp: in voltage mode an external R-C from Vin sets the feedforward ramp slope, and in current mode the RC resistor connects to REF for ramp compensation. |+| 2 | SS | passive | Soft-start pin charged by a 20 µA current source through an external capacitor, limiting duty during startup, with steady-state SS voltage of about 4.5 V and capacitor discharge on a fault. |+| 3 | DLMT | input | A resistor between this pin and AGND sets the maximum duty ratio; the pin is rated −0.3 V to 7 V with 2 mA maximum input current. |+| 4 | DT | input | An external resistor between this pin and AGND sets the overlap time delay between OUTM and OUTA. |+| 5 | RT | input | The total external resistance between RT and AGND sets the internal oscillator frequency, with a maximum oscillator frequency of 1 MHz. |+| 6 | AGND | power_in | Analog circuit ground reference for control and timing components, which should be tied to PGND at the return of the power stage. |+| 7 | COMP | input | Input to the PWM: an optocoupler between REF and COMP sources current, giving maximum duty at zero current and zero duty once the source current exceeds 850 µA; the pin is rated −0.3 V to 5.5 V and 1 mA maximum. |+| 8 | RES | passive | Restart timing pin: a capacitor to AGND sets the shutdown delay and hiccup restart delay, with a typical restart threshold of 1 V and peak of 4 V, and 32 charge/discharge cycles before restart. |+| 9 | OVP | input | When biased beyond 1.25 V, all pulses stop immediately and the controller resumes operation after 32 VRES charge/discharge cycles. |+| 10 | CS | input | Current sense input for current-mode control, adaptive dead time, cycle-by-cycle current limiting (typically 0.45 V) and short-circuit protection (typically 0.7 V over two consecutive clock pulses); the pin is rated −0.3 V to 7 V. |+| 11 | REF | power_out | Precision 5 V reference with a maximum output current of 12 mA, which must be bypassed with a 0.1 µF to 0.47 µF capacitor. |+| 12 | OTP | input | Over-temperature protection input connected to a voltage divider containing an NTC thermistor; the pin is rated −0.3 V to 7 V. |+| 13 | VCC | power_in | Positive supply input with an external energy-storage capacitor, rated 6.5 V to 20 V, where the startup current source is disabled once VCC reaches VCC(on) typically 9.5 V and the absolute maximum is 20 V. |+| 14 | OUTM | output | Main switch gate drive that can source 2 A and sink 3 A. |+| 15 | PGND | power_in | Power ground for the OUTM and OUTA gate drivers, to be tied to the power stage return with a short loop. |+| 16 | OUTA | output | Active clamp switch gate drive with adjustable leading and trailing edge overlap delay against OUTM, which can source 2 A and sink 1 A. |+| 17 | FLT/SD | bidirectional | Dual-function fault report and shutdown pin, implemented as an open-collector output with a 10 kΩ internal pull-up to REF. |+| 18 | REFA | power_out | Internally connected to REF, so it carries the 5 V reference internally and is not a separate reference source. |+| 19 | UVLO | input | Input undervoltage detector scaled by a resistor divider: the controller enters standby above 0.4 V, is enabled above 1.25 V, and has 20 µA internal hysteresis pull-down that is disabled once enabled. |+| 20 | SYNC | bidirectional | Bi-directional pin used to synchronize this controller or to synchronize another controller driven by this pin. |+| 21 | NC | unconnected | No connect, present for creepage distance. |+| 22 | VIN | power_in | High-voltage startup circuit input connected to the input line, with an operating range of 13 V to 120 V, a minimum charge current of 40 mA, and a continuous input voltage rating of −0.3 V to 120 V. |+| 23 | NC | unconnected | No connect, present for creepage distance. |+| 24 | VSCLAMP | input | Volt-second clamp: an external R-C divider from the input line generates a ramp compared to VSLIMIT (typically 1.5 V), terminating the OUTM pulse once exceeded; the pin is rated −0.3 V to 7 V and 0.5 mA maximum input current. |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | QFN-24-EP(4x4) |+| Category | Power Management (PMIC) |+| Pins | 25 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Supply Voltage Upper Regulation Level | VCC(on) | 9.1 | 9.5 | 9.9 | V | VCC increasing | 8 |+| Lower Regulation While Disabled | VCC(off1) | 9 | 9.4 | 9.8 | V | VCC decreasing | 8 |+| Lower Regulation While Enabled | VCC(off2) | 7.3 | 7.5 | 7.7 | V | VCC decreasing | 8 |+| Minimum Operating Voltage | VCC(MIN) | 6.2 | 6.5 | 6.8 | V | VCC decreasing | 8 |+| Reset Voltage | VCC(reset) | 6.1 | 6.4 | 6.7 | V | VCC decreasing | 8 |+| Startup Current | Istart | 40 | 55 | | mA | VCC = VCC(on), 0.2 V, Vin = 48 V | 8 |+| Supply Current, Disabled mode | ICC1 | | | 2 | mA | UVLO below 0.4 V | 8 |+| Supply Current, Standby | ICC2 | | | 2 | mA | VCC = 10 V, VUVLO = 1 V | 8 |+| Supply Current, No Switching | ICC3 | | | 4 | mA | VCC = 10 V, ICOMP = 850 μA | 8 |+| Supply Current, Operating | ICC4 | | | 5 | mA | f = 200 kHz, COUTM = COUTA = open | 8 |+| Reference Voltage | VREF | 4.9 | 5 | 5.1 | V | IREF = 0 mA | 8 |+| Source Current | IREF(MAX) | 12 | | | mA | VREF = 4.75 V | 8 |+| Standby Decreasing | VSTBY | 0.2 | 0.3 | 0.4 | V | VUVLO decreasing | 8 |+| Enable Threshold | Venable | 1.23 | 1.25 | 1.27 | V | VUVLO increasing | 8 |+| Pull-Down Current in Standby Mode | ISTBY | 18 | 20 | 22 | μA | VUVLO = Venable, 0.1 V; VSHDN < VUVLO < Venable | 8 |+| Main Gate Current Capability, Source | IOUTM(SRC) | 2 | | | A | VOUTM = 4 V | 9 |+| Main Gate Current Capability, Sink | IOUTM(SNK) | 3 | | | A | VOUTM = 4 V, VCC = 7.5 V, ICOMP = 850 μA | 9 |+| Active Clamp Gate Current Capability, Source | IOUTA(SRC) | 2 | | | A | VOUTA = 4 V | 9 |+| Active Clamp Gate Current Capability, Sink | IOUTA(SNK) | 1 | | | A | VOUTA = 4 V, VCC = 7.5 V | 9 |+| Average Current Limit Threshold | VILIM(ave) | 288 | 300 | 312 | mV | | 9 |+| Cycle by Cycle Current Limit Threshold | VILIM | 432 | 450 | 468 | mV | | 9 |+| Short Circuit Current Limit Threshold | VILIM(SC) | 679 | 700 | 721 | mV | | 9 |+| Current Sourced by CS high line Over Power Protection current | CSOVPH | 90 | 100 | 110 | μA | VUVLO = 2.8 V | 9 |+| Overtemperature Detection Threshold | VOTP(TH) | 1.23 | 1.25 | 1.27 | V | VOTP increasing | 10 |+| Overvoltage Detection Threshold | VOVP(TH) | 1.23 | 1.25 | 1.27 | V | VOVP increasing | 10 |+| Oscillator Frequency (set 1) | fOSC1 | 186 | 200 | 214 | kHz | tD ≈ 100 ns, RT = 42.2 kΩ, RDT = 69.8 kΩ, RDLMT = 47.5 kΩ | 11 |+| Oscillator Frequency (set 2) | fOSC2 | 558 | 600 | 642 | kHz | tD ≈ 75 ns, RT = 13 kΩ, RDT = 52.3 kΩ, RDLMT = 17 kΩ | 11 |+| Maximum Duty Ratio (set 1a) | D(MAX1a) | 76.5 | 80.5 | 84.5 | % | RT = 15.4 kΩ, RDT = 69.8 kΩ, RDLMT = 75 kΩ | 11 |+| Maximum Duty Ratio (set 2a) | D(MAX2a) | 47.8 | 50.3 | 52.8 | % | RT = 42.2 kΩ, RDT = 69.8 kΩ, RDLMT = 47.5 kΩ | 11 |+| Minimum Duty Ratio | D(MIN) | | | 0 | % | ICOMP = 850 μA | 11 |+| Volt Second Limit Voltage Threshold | VSLIMIT | 1.44 | 1.5 | 1.56 | V | ICOMP = 0 μA | 11 |+| Overlap Delay Range | tD(range) | 20 | | 500 | ns | | 11 |+| Overlap Delay from OUTA to OUTM rising Edges (tDa) | tDa | 84 | 112 | 140 | ns | RDT = 52.3 kΩ, VCS = 0.4 V | 11 |+| Overlap Delay from OUTA to OUTM rising Edges (tDc) | tDc | 112 | 150 | 187 | ns | RDT = 69.8 kΩ, VCS = 0.4 V | 11 |+| Overlap Delay from OUTA to OUTM rising Edges (tDe) | tDe | 440 | 587 | 734 | ns | RDT = 274 kΩ, VCS = 0.4 V | 11 |+| Thermal Shutdown Temperature | TSHDN | 150 | 165 | | C | Temperature increasing | 12 |+| Reference Undervoltage Threshold | VREF(UVLO) | 4.5 | | 4.75 | V | VREF increasing | 8 |+| Active Clamp Driver Maximum Current, source | IOUTA(SRC) | | | 2 | A | | 7 |+| Active Clamp Driver Maximum Current, sink | IOUTA(SNK) | | | 1 | A | | 7 |+| Current Sense Input Voltage | VCS | -0.3 | | 7 | V | | 7 |+| Current Sense Peak Input Current | ICS | | | 0.5 | A | | 7 |+| Soft-Start Input Voltage | VSS | -0.3 | | 7 | V | | 7 |+| Restart Input Voltage | VRES | -0.3 | | 7 | V | | 7 |+| Restart Peak Input Current | IRES | | | 0.1 | A | | 7 |+| FLT/SD Input Voltage | VFLT/SD | -0.3 | | 7 | V | | 7 |+| FLT/SD Peak Input Current | IFLT/SD | | | 0.1 | A | | 7 |+| Deadtime Input Voltage | VDT | -0.3 | | 7 | V | | 7 |+| Maximum Duty Ratio Control Input Voltage | VDLMT | -0.3 | | 7 | V | | 7 |+| Maximum Duty Ratio Control Input Current | IDLMT | | | 2 | mA | | 7 |+| Maximum Operating Junction Temperature | TJ | -40 | | 150 | C | | 7 |+| Storage Temperature Range | TSTG | -60 | | 150 | C | | 7 |+| Lead Temperature (Soldering, 10 s) | TL(MAX) | | | 300 | C | | 7 |+| Power Dissipation | PD | | | 760 | mW | TA = 25C, 1 oz Cu, 100 mm2 2-layer PCB | 7 |+| ESD Capability Human Body Model | | 2000 | | | V | JESD22-A114F | 7 |+| ESD Capability Charge Device Model | | 1500 | | | V | JESD22-C101F | 7 |+| Thermal Resistance, Junction to Ambient | RθJA | | 131 | | C/W | 1 oz Cu (35 μm) 2-layer, 100 mm2 PCB | 7 |+| Thermal Resistance, Junction to Case (as printed) | RθJA | | 115 | | C/W | 2 oz Cu (70 μm) 2-layer, 100 mm2 PCB | 7 |+| Junction to Top | ψθJT | | 22 | | C/W | 1 oz Cu (35 μm) 2-layer, 100 mm2 PCB | 7 |+| Junction to Board | ψθJB | | 5.4 | | C/W | 1 oz Cu (35 μm) 2-layer, 100 mm2 PCB | 7 |+| Vcc Range | VCC | 6.5 | | 20 | V | | 1 |++## CAD (KiCad official)++- Symbol: `NCP1566MNTXG`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`+- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `ncp1566mntxg-etched.step` / `ncp1566mntxg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncp1566mntxg.step` / `ncp1566mntxg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913644977864704) (38 pp, sha256 `7e90dffb7a03ef59`, retrieved 2026-10-19, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncp1566mntxg-datasheet.pdf)
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This controller integrates all the necessary control and protection functions to implement an isolated active clamp forward or asymmetric half-bridge converter. It integrates a high-voltage startup bias regulator. The NCP1566 has a line undervoltage detector, cycle-by-cycle current limiting, line voltage dependent maximum duty ratio limit, over voltage protection, and programmable overtemperature protection using an external thermistor. It also includes a dual-function FLT/SD pin used for communicating the presence of a fault but also for shutting down the controller. A dedicated dual-function synchronization pin eases operations when associating bricks together.</rdf:li>+ </rdf:Alt>+ </dc:description>+ <pdf:Producer>Acrobat Distiller 18.0 (Windows)</pdf:Producer>+ <pdf:Keywords/>+ <xmpMM:DocumentID>uuid:1d544ee3-1b91-449a-b3ce-e223260a429c</xmpMM:DocumentID>+ <xmpMM:InstanceID>uuid:e851f0a3-a225-4b28-8391-9197596880be</xmpMM:InstanceID>+ </rdf:Description>+ </rdf:RDF>+</x:xmpmeta>+ + + + + + + + + + + + + + + + + + + + + +<?xpacket end="w"?> +endstream+endobj+6 0 obj+<<+/Annots [47 0 R 48 0 R]+/Contents [49 0 R 50 0 R 51 0 R 52 0 R 53 0 R 54 0 R 55 0 R 56 0 R]+/CropBox [0.0 0.0 612.0 792.0]+/MediaBox [0.0 0.0 612.0 792.0]+/Parent 2 0 R+/Resources 57 0 R+/Rotate 0+/Type /Page+>>+endobj+7 0 obj+<<+/Annots [58 0 R]+/Contents 59 0 R+/CropBox [0.0 0.0 612.0 792.0]+/MediaBox [0.0 0.0 612.0 792.0]+/Parent 2 0 R+/Resources 60 0 R+/Rotate 0+/Type /Page+>>+endobj+8 0 obj+<<+/Annots [61 0 R]+/Contents 62 0 R+/CropBox [0.0 0.0 612.0 792.0]+/MediaBox [0.0 0.0 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