NCP1399APDR2G

@@ -0,0 +1,67 @@+# NCP1399APDR2G++**onsemi** · AC-DC Controllers and Regulators · SOIC-16-EP++NCP1399APDR2G from onsemi, in a SOIC-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | HV | power_in | High-voltage startup current source input. Connects to the rectified AC line or bulk capacitor (up to 600 V) to implement the internal startup current source and Dynamic Self-Supply (DSS). |+| 3 | VBULK/PFCFB | input | Bulk voltage monitoring input. Receives a resistor-divided bulk-voltage sample to implement Brown-Out protection (0 to 5.5 V absolute max). |+| 4 | SKIP/REM | input | Skip threshold adjust / Off-mode (remote) control input. A resistor to GND sets the skip-in threshold (NCP1399Ay). Pulled up by external auxiliary source to activate off-mode/standby; pull-down by optocoupler deactivates off-mode (NCP1399By). |+| 5 | LLCFB | input | LLC feedback input. Defines operating frequency based on load; controls skip-mode entry under light load and, for NCP1399Ay, activates off-mode operation. |+| 6 | LLCCS | input | LLC current-sense input. Senses divided resonant-capacitor voltage to perform on-time modulation, out-of-resonance switching protection, over-current protection, and secondary-side short-circuit protection (-5 to +5 V abs max). |+| 7 | OTP/OVP | input | Combined over-temperature and over-voltage protection input. A single pin implements both OTP and OVP latch triggers (0 to 5.5 V abs max). |+| 8 | PON/OFF | input | PFC turn-off feedback-level adjust. Sets the FB threshold below which the external PFC stage is disabled, enabling load-dependent PFC on/off control. |+| 9 | PFCMODE | output | PFC mode / external HV switch control output. Provides supply voltage to the PFC front-stage controller and/or enables the VBULK sensing network HV switch. |+| 10 | VCC | power_in | Controller supply input. Accepts up to 20 V; VCC_ON ~15.8 V (or ~12 V on AL/AM/AR/AS variants), VCC_OFF ~9.5 V UVLO. Operating current 5.4 mA typ at 100 kHz. |+| 11 | GND | power_in | Analog ground. Common return for adjustment components, sensing networks, and low-side driver output. |+| 12 | MLOWER | output | Low-side gate driver output. Drives the lower MOSFET of the half-bridge; output swings 0 to VCC (up to ~20 V). |+| 14 | MUPPER | output | High-side (floating) gate driver output. Drives the upper MOSFET of the half-bridge, referenced to HB with supply from VBOOT. |+| 15 | HB | power_in | Half-bridge connection / high-side driver return. Connects to the switching node between the two half-bridge MOSFETs; withstands up to ~600 V and dV/dt up to 50 V/ns. |+| 16 | VBOOT | power_in | Bootstrap supply pin. Provides the floating VCC for the high-side driver referenced to HB (VBOOT_ON ~9 V, VBOOT_OFF ~8.2 V, up to 620 V absolute). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-16-EP |+| Category | PMIC |+| Pins | 14 |++## Ordering variants++- `NCP1399APDR2GAADR2G`+- `NCP1399APDR2GBADR2G`+- `NCP1399APDR2GACDR2G`+- `NCP1399APDR2GAFDR2G`+- `NCP1399APDR2GAGDR2G`+- `NCP1399APDR2GAHDR2G`+- `NCP1399APDR2GAIDR2G`+- `NCP1399APDR2GAJDR2G`+- `NCP1399APDR2GAKDR2G`+- `NCP1399APDR2GALDR2G`+- `NCP1399APDR2GAMDR2G`+- `NCP1399APDR2GANDR2G`+- `NCP1399APDR2GAPDR2G`+- `NCP1399APDR2GARDR2G`+- `NCP1399APDR2GASDR2G`++## CAD (KiCad official)++- Symbol: `NCP1399APDR2G`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-EP (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncp1399ap-d.pdf) (45 pp, sha256 `a9c71c608fac5987`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ncp1399apdr2g-datasheet.pdf)

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