component
NCP1252EDR2G
Public Made by Adomby adom
onsemi AC-DC Controllers and Regulators, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+11−8@@ -32,25 +32,25 @@ "number": "1", "name": "FB", "type": "input",- "description": "Feedback input. Directly connects to an optocoupler collector. Internally pulled up (~3.5 k\u03a9) to Vdd; the FB voltage is divided by 3 to form the current setpoint (VILIM = 1 V). Max FB current 1.5 mA."+ "description": "Feedback input. Directly connects to an optocoupler collector. Internally pulled up (~3.5 kΩ) to Vdd; the FB voltage is divided by 3 to form the current setpoint (VILIM = 1 V). Max FB current 1.5 mA." }, { "number": "2", "name": "BO", "type": "input",- "description": "Brown-Out input. Monitors an image of the input bulk voltage via a resistor divider to provide brown-out protection. Threshold VBO = 1 V typ; internal 10 \u00b5A hysteresis current source."+ "description": "Brown-Out input. Monitors an image of the input bulk voltage via a resistor divider to provide brown-out protection. Threshold VBO = 1 V typ; internal 10 µA hysteresis current source." }, { "number": "3", "name": "CS", "type": "input",- "description": "Current Sense input. Monitors the primary MOSFET current through a sense resistor and sets the ramp-compensation amplitude. Cycle-by-cycle limit VILIM = 1 V; fault threshold FCS = 1 V; 160 ns leading-edge blanking; internal ramp comp Rramp \u2248 26.5 k\u03a9."+ "description": "Current Sense input. Monitors the primary MOSFET current through a sense resistor and sets the ramp-compensation amplitude. Cycle-by-cycle limit VILIM = 1 V; fault threshold FCS = 1 V; 160 ns leading-edge blanking; internal ramp comp Rramp ≈ 26.5 kΩ." }, { "number": "4", "name": "RT", "type": "passive",- "description": "Timing element. A resistor to ground fixes the switching frequency (RT = 43 k\u03a9 \u2192 fOSC \u2248 100 kHz; RT = 8.5 k\u03a9 \u2192 fOSC \u2248 500 kHz). Frequency is jittered \u00b15% at 3.33 ms period."+ "description": "Timing element. A resistor to ground fixes the switching frequency (RT = 43 kΩ → fOSC ≈ 100 kHz; RT = 8.5 kΩ → fOSC ≈ 500 kHz). Frequency is jittered ±5% at 3.33 ms period." }, { "number": "5",@@ -62,19 +62,19 @@ "number": "6", "name": "DRV", "type": "output",- "description": "Gate driver output to the external power MOSFET. +500 mA source / -800 mA sink capability; source resistance 10 \u03a9 typ, sink 6 \u03a9 typ; clamped at 15 V typ (max 18 V) to protect the MOSFET gate."+ "description": "Gate driver output to the external power MOSFET. +500 mA source / -800 mA sink capability; source resistance 10 Ω typ, sink 6 Ω typ; clamped at 15 V typ (max 18 V) to protect the MOSFET gate." }, { "number": "7", "name": "VCC", "type": "power_in",- "description": "Main supply pin. Operating range 8 V to 28 V (30 V transient <10 ms for IVCC<20 mA). For the E version, VCC(on) \u2248 14 V, VCC(off) \u2248 9 V with 5 V hysteresis (auto-recovery UVLO). Max injected current 20 mA."+ "description": "Main supply pin. Operating range 8 V to 28 V (30 V transient <10 ms for IVCC<20 mA). For the E version, VCC(on) ≈ 14 V, VCC(off) ≈ 9 V with 5 V hysteresis (auto-recovery UVLO). Max injected current 20 mA." }, { "number": "8", "name": "SSTART", "type": "passive",- "description": "Soft-start pin. A capacitor to ground sets the soft-start duration (charge current ISS = 10 \u00b5A typ, VSS = 4 V). The pin is held to ground during the internal start-up delay timer (no delay for E version)."+ "description": "Soft-start pin. A capacitor to ground sets the soft-start duration (charge current ISS = 10 µA typ, VSS = 4 V). The pin is held to ground during the internal start-up delay timer (no delay for E version)." } ], "provenance": {@@ -138,5 +138,8 @@ "docs/ncp1252edr2g-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }