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NCH-RSL10-101Q48-ABG
Public Made by Adomby adom
onsemi RF Transceiver ICs, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+140docs/hero.pngdocs/nch-rsl10-101q48-abg-datasheet.pdf+4769nch-rsl10-101q48-abg-etched.glbnch-rsl10-101q48-abg-hero.glbnch-rsl10-101q48-abg-hero.overlay.json+1153nch-rsl10-101q48-abg.glbnch-rsl10-101q48-abg.kicad_mod+691nch-rsl10-101q48-abg.kicad_sym+209nch-rsl10-101q48-abg.lbr+255nch-rsl10-101q48-abg.step+17040README.mdadded+140@@ -0,0 +1,140 @@+# NCH-RSL10-101Q48-ABG++**onsemi** · RF Transceiver ICs · QFN-48-EP(6x6)++NCH-RSL10-101Q48-ABG from onsemi, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RF | bidirectional | RF signal input/output to the antenna; single-ended 50 ohm port with on-chip matching network. |+| 2 | VDDPA | power_out | Radio power amplifier supply from its regulator, operating range 1.05 to 1.68 V; the regulator can be disabled if high-power transmit is not needed. |+| 3 | VSSPA | power_in | Radio power amplifier ground. |+| 4 | AOUT | output | Analog test output pin, which is also one of the inputs read by the on-chip ADC. |+| 5 | VDDA | power_out | Charge pump output supplying the analog blocks and flash memory, decoupled with 1 uF to VSSA. |+| 6 | CAP1 | passive | Pump capacitor connection; 1 uF pump capacitor between CAP0 and CAP1. |+| 7 | CAP0 | passive | Pump capacitor connection; 1 uF pump capacitor between CAP0 and CAP1. |+| 8 | VSSA | power_in | Analog ground. |+| 9 | VBAT | power_in | Battery input voltage, operating range 1.18 to 3.3 V (1.1 V minimum under restricted conditions), absolute maximum 3.63 V. |+| 10 | VDC | power_out | DC-DC converter output to the external LC filter (2.2 uH) used in buck mode. |+| 11 | RES | input | Reserved pin, pull-down 250 kohm; not described for user use. |+| 12 | VCC | power_out | DC-DC filtered output, decoupled with low-ESR 2.2 uF (or 4.7 uF) to VSSA. |+| 13 | XTAL32_OUT | output | Output pin of the 32 kHz crystal oscillator. |+| 14 | XTAL32_IN | input | Input pin of the 32 kHz crystal oscillator, with internal load capacitance trimmable from 0 to 25.2 pF so no external load capacitors are required. |+| 15 | WAKEUP | input | Wake-up input for power modes. |+| 16 | NRESET | input | Reset pin powered from VDDO, with 200 kohm pull-up. |+| 17 | VPP | bidirectional | Flash high voltage access pin. |+| 18 | DIO[0] | bidirectional | Digital input/output 0, also ADC 0, Wakeup 0 and STANDBYCLK input, with selectable pull-up (10 kohm to 250 kohm) or pull-down. |+| 19 | VDDC | power_out | LDO output for the core logic supply, operating range 0.92 to 1.32 V (1.15 V typical). |+| 20 | DIO[1] | bidirectional | Digital input/output 1, also ADC 1, Wakeup 1 and STANDBYCLK input, with selectable pull-up or pull-down. |+| 21 | VDDM | power_out | LDO output for the memories supply, operating range 1.05 to 1.32 V (1.15 V typical). |+| 22 | DIO[9] | bidirectional | Digital input/output 9 with Schmitt-trigger input and selectable pull-up or pull-down. |+| 23 | DIO[2] | bidirectional | Digital input/output 2, also ADC 2, Wakeup 2 and STANDBYCLK input, with selectable pull-up or pull-down. |+| 24 | DIO[4] | bidirectional | Digital input/output 4 with selectable pull-up or pull-down. |+| 25 | DIO[3] | bidirectional | Digital input/output 3, also ADC 3, Wakeup 3 and STANDBYCLK input, with selectable pull-up or pull-down. |+| 26 | DIO[8] | bidirectional | Digital input/output 8 with selectable pull-up or pull-down. |+| 27 | DIO[5] | bidirectional | Digital input/output 5 with selectable pull-up or pull-down. |+| 28 | VSSD | power_in | Digital ground for I/O and core. |+| 29 | DIO[6] | bidirectional | Digital input/output 6 with selectable pull-up or pull-down. |+| 30 | DIO[7] | bidirectional | Digital input/output 7 with selectable pull-up or pull-down. |+| 31 | EXTCLK | input | External clock input with pull-up. |+| 32 | DIO[10] | bidirectional | Digital input/output 10 with selectable pull-up or pull-down. |+| 33 | JTCK | bidirectional | CM3-JTAG test clock, with pull-up. |+| 34 | JTMS | bidirectional | CM3-JTAG test mode state, with pull-up. |+| 35 | VSSD | power_in | Digital ground for I/O and core. |+| 36 | VDDO | power_in | Digital I/O supply, operating range 1.1 to 3.3 V, absolute maximum 3.63 V. |+| 37 | DIO[12] | bidirectional | Digital input/output 12 with selectable pull-up or pull-down. |+| 38 | DIO[11] | bidirectional | Digital input/output 11 with selectable pull-up or pull-down. |+| 39 | DIO[13] | bidirectional | Digital input/output 13, also CM3-JTAG test reset, with selectable pull-up or pull-down. |+| 40 | DIO[15] | bidirectional | Digital input/output 15, also CM3-JTAG test data out, with selectable pull-up or pull-down. |+| 41 | DIO[14] | bidirectional | Digital input/output 14, also CM3-JTAG test data in, with selectable pull-up or pull-down. |+| 42 | VSS | power_in | Substrate connection for the RF part; should be connected to VSSRF at PCB level. |+| 43 | XTAL48_N | passive | Negative input of the 48 MHz crystal oscillator; internal load capacitors, no external load capacitors required. |+| 44 | XTAL48_P | passive | Positive input of the 48 MHz crystal oscillator; fundamental 48 MHz crystal with ESR 20 to 80 ohm. |+| 45 | VDDSYN_SW | power_in | Supply pin for the radio synthesizer. |+| 46 | VSSRF | power_in | RF analog ground. |+| 47 | VDDRF_SW | power_in | Supply pin for the RF front-end. |+| 48 | VDDRF | power_out | LDO output for the radio voltage supply, operating range 1.00 to 1.32 V (1.10 V typical). |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | QFN-48-EP(6x6) |+| Category | RF And Wireless |+| Pins | 49 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Power supply voltage | VBAT | | | 3.63 | V | | 3 |+| I/O supply voltage | VDDO | | | 3.63 | V | | 3 |+| RF front-end ground | VSSRF | -0.3 | | | V | | 3 |+| Analog ground | VSSA | -0.3 | | | V | | 3 |+| Digital core and I/O ground | VSSD | -0.3 | | | V | | 3 |+| Functional temperature range | T functional | -40 | | 85 | °C | | 3 |+| Storage temperature range | T storage | -40 | | 85 | °C | | 3 |+| Supply voltage operating range | VBAT | 1.18 | 1.25 | 3.3 | V | Input supply voltage on VBAT pin (Note 2) | 4 |+| Digital I/O supply | VDDO | 1.1 | 1.25 | 3.3 | V | | 6 |+| Supply voltage: operating range (VDDC) | VDDC | 0.92 | 1.15 | 1.32 | V | | 5 |+| Supply voltage: trimming range (VDDC) | VDDCRANGE | 0.75 | | 1.38 | V | | 5 |+| Supply voltage: operating range (VDDM) | VDDM | 1.05 | 1.15 | 1.32 | V | | 5 |+| Supply voltage: trimming range (VDDM) | VDDMRANGE | 0.75 | | 1.38 | V | | 5 |+| Supply voltage: operating range (VDDRF) | VDDRF | 1 | 1.1 | 1.32 | V | | 5 |+| Supply voltage: trimming range (VDDRF) | VDDRFRANGE | 0.75 | | 1.38 | V | | 5 |+| Supply voltage: operating range (VDDPA) | VDDPA | 1.05 | 1.3 | 1.68 | V | | 5 |+| Supply voltage: trimming range (VDDPA) | VDDPARANGE | 1.05 | | 1.68 | V | | 5 |+| VBAT range when the DC-DC converter is active | DCDC IN_RANGE | 1.4 | | 3.3 | V | VBAT range when the DC-DC converter is active (Note 7) | 6 |+| VBAT range when the LDO is active | LDO IN_RANGE | 1.1 | | 3.3 | V | | 6 |+| Output voltage: trimming range | DCDC OUT_RANGE | 1.1 | 1.2 | 1.32 | V | | 6 |+| POR voltage | VBATPOR | 0.4 | 0.8 | 1 | V | | 6 |+| Data rate FSK / MSK / GFSK | RFSK | 62.5 | 1000 | 3000 | kbps | OQPSK as MSK | 6 |+| On-air data rate | | 250 | | 2000 | kbps | GFSK | 6 |+| Equiv. series resistance | ESRXTAL | 20 | | 80 | | RSL10 has internal load capacitors, additional external capacitors are not required | 6 |+| Differential equivalent load capacitance | CLXTAL | 6 | 8 | 10 | pF | Internal load capacitors (NO EXTERNAL LOAD CAPACITORS REQUIRED) | 6 |+| Crystal settling time | | 0.5 | | 1.5 | ms | | 6 |+| Frequency range | FRF | 2360 | | 2500 | MHz | Supported carrier frequencies | 6 |+| PLL Settling time, RX | tPLL_RX | 15 | | 25 | s | RX Mode | 6 |+| PLL Settling time, TX | tPLL_TX | 5 | | 10 | s | TX mode, BLE modulation | 6 |+| Transmit power range | | -17 | | 6 | dBm | BLE or 802.15.4 OQPSK | 7 |+| Transmit power accuracy | | -1.5 | | 1 | dB | Tx power 3 dBm. Full band. Relative to the typical value. | 7 |+| Transmit power accuracy | | -1.5 | | 1.5 | dB | Tx power 0 dBm. Full band. Relative to the typical value. | 7 |+| Power in 2nd harmonic | | -31 | | -18 | dBm | 0 dBm mode. 50 for “Typ” value. | 7 |+| Power in 3rd harmonic | | -40 | | -31 | dBm | 0 dBm mode. 50 for “Typ” value. | 7 |+| Power in 4th harmonic | | -49 | | -42 | dBm | 0 dBm mode. 50 for “Typ” value. | 7 |+| ADC resolution | ADCRES | 8 | 12 | 14 | bits | | 7 |+| ADC input voltage range | ADCRANGE | 0 | | 2 | V | | 7 |+| ADC INL | ADCINL | -2 | | 2 | mV | | 7 |+| ADC DNL | ADCDNL | -1 | | 1 | mV | | 7 |+| ADC channel sampling frequency | ADCCH_SF | 0.0195 | | 6.25 | kHz | For the 8 channels sequentially, SLOWCLK = 1 MHz | 7 |+| 32 kHz on-chip RC oscillator untrimmed frequency | FreqUNTR | 20 | 32 | 50 | kHz | | 7 |+| 3 MHz on-chip RC oscillator untrimmed frequency | FreqUNTR | 2 | 3 | 5 | MHz | | 7 |+| 32 kHz crystal oscillator startup time | | 1 | | 3 | s | | 8 |+| Internal load trimming range | | 0 | | 25.2 | pF | Steps of 0.4 pF | 8 |+| Duty cycle (32 kHz crystal oscillator) | | 40 | 50 | 60 | % | | 8 |+| Voltage level for high input | VIH | 2 | | | V | With VDDO = 2.97 V, 3.3 V, nominal: 3.0 V Logic | 8 |+| Voltage level for low input | VIL | | | 0.8 | V | With VDDO = 2.97 V, 3.3 V, nominal: 3.0 V Logic | 8 |+| DIO drive strength | IDIO | 2 | 12 | 12 | mA | | 8 |++## CAD (KiCad official)++- Symbol: `NCH-RSL10-101Q48-ABG`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm`+- 3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `nch-rsl10-101q48-abg-etched.step` / `nch-rsl10-101q48-abg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nch-rsl10-101q48-abg.step` / `nch-rsl10-101q48-abg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914889650294784) (21 pp, sha256 `126c736dbe1f86df`, retrieved 2026-10-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/nch-rsl10-101q48-abg-datasheet.pdf)
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nch-rsl10-101q48-abg.glbadded⋯ 1 unchanged line ⋯
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