component
NB3H83905CMNG
Public Made by Adomby adom
onsemi Buffer/Driver/Transceiver, QFN-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+113docs/hero.pngdocs/nb3h83905cmng-datasheet.pdf+6033nb3h83905cmng-etched.glbnb3h83905cmng-hero.glbnb3h83905cmng-hero.overlay.json+537nb3h83905cmng.glbnb3h83905cmng.kicad_mod+319nb3h83905cmng.kicad_sym+97nb3h83905cmng.lbr+171nb3h83905cmng.step+5430package.json+316page.json+322viewers/footprint.html+1viewers/symbol.html+1README.mdadded+113@@ -0,0 +1,113 @@+# NB3H83905CMNG++**onsemi** · Buffer/Driver/Transceiver · QFN-20(4x4)++NB3H83905CMNG from onsemi, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground supply pin; all GND, VDD and VDDO pins must be externally connected to the power supply to guarantee proper operation. |+| 2 | GND | power_in | Ground supply pin; all GND, VDD and VDDO pins must be externally connected to the power supply to guarantee proper operation. |+| 3 | BCLK0 | output | Buffered LVTTL/LVCMOS clock output in the ENABLE1-controlled group BCLK0:4; the outputs drive 50 Ω series or parallel terminated transmission lines. |+| 4 | VDDO | power_in | Positive supply for the outputs, 1.8 V ±0.2 V, 2.5 V ±5% or 3.3 V ±5%, which must not exceed VDD; bypass to GND with 0.01 µF. |+| 5 | BCLK1 | output | Buffered LVTTL/LVCMOS clock output in the ENABLE1-controlled group BCLK0:4; the outputs drive 50 Ω series or parallel terminated transmission lines. |+| 6 | GND | power_in | Ground supply pin; all GND, VDD and VDDO pins must be externally connected to the power supply to guarantee proper operation. |+| 7 | GND | power_in | Ground supply pin; all GND, VDD and VDDO pins must be externally connected to the power supply to guarantee proper operation. |+| 8 | BCLK2 | output | Buffered LVTTL/LVCMOS clock output in the ENABLE1-controlled group BCLK0:4; the outputs drive 50 Ω series or parallel terminated transmission lines. |+| 9 | VDD | power_in | Core supply, 1.8 V ±0.2 V, 2.5 V ±5% or 3.3 V ±5%, which must be ≥ VDDO; bypass to GND with 0.01 µF. |+| 10 | BCLK3 | output | Buffered LVTTL/LVCMOS clock output in the ENABLE1-controlled group BCLK0:4; the outputs drive 50 Ω series or parallel terminated transmission lines. |+| 11 | GND | power_in | Ground supply pin; all GND, VDD and VDDO pins must be externally connected to the power supply to guarantee proper operation. |+| 12 | GND | power_in | Ground supply pin; all GND, VDD and VDDO pins must be externally connected to the power supply to guarantee proper operation. |+| 13 | BCLK4 | output | Buffered LVTTL/LVCMOS clock output in the ENABLE1-controlled group BCLK0:4; the outputs drive 50 Ω series or parallel terminated transmission lines. |+| 14 | VDDO | power_in | Positive supply for the outputs, 1.8 V ±0.2 V, 2.5 V ±5% or 3.3 V ±5%, which must not exceed VDD; bypass to GND with 0.01 µF. |+| 15 | BCLK5 | output | Buffered LVTTL/LVCMOS clock output controlled by ENABLE2; the output drives 50 Ω series or parallel terminated transmission lines. |+| 16 | NC | unconnected | No connect; no internal connection to the die. |+| 17 | ENABLE1 | input | Synchronous LVTTL/LVCMOS enable for outputs BCLK0 to BCLK4, 5 V tolerant, with an internal pull-up so it defaults HIGH when left open. |+| 18 | XTAL_IN/CLK | input | Crystal oscillator input or single-ended LVCMOS clock input; accepts a crystal from 3 MHz to 40 MHz or a clock up to 100 MHz. |+| 19 | XTAL_OUT | output | Crystal oscillator output that drives the crystal; the recommended crystal is 10 to 40 MHz fundamental AT-cut with 16 to 20 pF load capacitance. |+| 20 | ENABLE2 | input | Synchronous LVTTL/LVCMOS enable for output BCLK5, 5 V tolerant, with an internal pull-up so it defaults HIGH when left open. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | QFN-20(4x4) |+| Category | Logic ICs |+| Pins | 21 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Positive Power Supply (VDDx) | VDDx | | | 4.6 | V | GND = 0 V | 4 |+| Input Voltage (VI) | VI | -0.5 | | | V | -0.5 <= VI <= VDD + 0.5 V (upper bound not numeric) | 4 |+| Operating Temperature Range, Industrial | TA | -40 | | 85 | °C | | 4 |+| Storage Temperature Range | Tstg | -65 | | 150 | °C | | 4 |+| IDD Core Quiescent Power Supply Current | IDD | | | 10 | mA | VDD=VDDO=3.135-3.465 V; ENABLEx = LOW | 5 |+| IDDO Output Quiescent Power Supply Current | IDDO | | | 5 | mA | VDD=VDDO=3.135-3.465 V; ENABLEx = LOW | 5 |+| Input HIGH Voltage ENABLEx, XTAL_IN/CLK | VIH | 2 | | | V | VDD=VDDO=3.135-3.465 V (max printed as VDD + 0.3 V) | 5 |+| Input LOW Voltage ENABLEx, XTAL_IN/CLK | VIL | -0.3 | | 0.8 | V | VDD=VDDO=3.135-3.465 V | 5 |+| Output HIGH Voltage | VOH | 2.6 | | | V | VDD=VDDO=3.135-3.465 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 5 |+| Output LOW Voltage | VOL | | | 0.5 | V | VDD=VDDO=3.135-3.465 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 5 |+| IDD Core Quiescent Power Supply Current | IDD | | | 8 | mA | VDD=VDDO=2.375-2.625 V; ENABLEx = LOW | 5 |+| IDDO Output Quiescent Power Supply Current | IDDO | | | 4 | mA | VDD=VDDO=2.375-2.625 V; ENABLEx = LOW | 5 |+| Input HIGH Voltage ENABLEx, XTAL_IN/CLK | VIH | 1.7 | | | V | VDD=VDDO=2.375-2.625 V (max printed as VDD + 0.3 V) | 5 |+| Input LOW Voltage ENABLEx, XTAL_IN/CLK | VIL | -0.3 | | 0.7 | V | VDD=VDDO=2.375-2.625 V | 5 |+| Output HIGH Voltage | VOH | 2 | | | V | VDD=VDDO=2.375-2.625 V; IOH = -1 mA | 5 |+| Output HIGH Voltage | VOH | 1.8 | | | V | VDD=VDDO=2.375-2.625 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 5 |+| Output LOW Voltage | VOL | | | 0.4 | V | VDD=VDDO=2.375-2.625 V; IOL = 1 mA | 5 |+| Output LOW Voltage | VOL | | | 0.45 | V | VDD=VDDO=2.375-2.625 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 5 |+| IDD Core Quiescent Power Supply Current | IDD | | | 5 | mA | VDD=VDDO=1.6-2.0 V; ENABLEx = LOW | 5 |+| IDDO Output Quiescent Power Supply Current | IDDO | | | 3 | mA | VDD=VDDO=1.6-2.0 V; ENABLEx = LOW | 5 |+| Input LOW Voltage ENABLEx, XTAL_IN/CLK | VIL | -0.3 | | | V | VDD=VDDO=1.6-2.0 V (max printed as 0.35 * VDD) | 5 |+| Output LOW Voltage | VOL | | | 0.35 | V | VDD=VDDO=1.6-2.0 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 5 |+| IDD Core Quiescent Power Supply Current | IDD | | | 10 | mA | VDD=3.135-3.465 V; VDDO=2.375-2.625 V; ENABLEx = LOW | 6 |+| IDDO Output Quiescent Power Supply Current | IDDO | | | 4 | mA | VDD=3.135-3.465 V; VDDO=2.375-2.625 V; ENABLEx = LOW | 6 |+| Input HIGH Voltage ENABLEx, XTAL_IN/CLK | VIH | 2 | | | V | VDD=3.135-3.465 V; VDDO=2.375-2.625 V (max printed as VDD + 0.3 V) | 6 |+| Input LOW Voltage ENABLEx, XTAL_IN/CLK | VIL | -0.3 | | 0.8 | V | VDD=3.135-3.465 V; VDDO=2.375-2.625 V | 6 |+| Output HIGH Voltage | VOH | 2 | | | V | VDD=3.135-3.465 V; VDDO=2.375-2.625 V; IOH = -1 mA | 6 |+| Output HIGH Voltage | VOH | 1.8 | | | V | VDD=3.135-3.465 V; VDDO=2.375-2.625 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 6 |+| Output LOW Voltage | VOL | | | 0.4 | V | VDD=3.135-3.465 V; VDDO=2.375-2.625 V; IOL = 1 mA | 6 |+| Output LOW Voltage | VOL | | | 0.45 | V | VDD=3.135-3.465 V; VDDO=2.375-2.625 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 6 |+| IDDO Output Quiescent Power Supply Current | IDDO | | | 3 | mA | VDD=3.135-3.465 V; VDDO=1.6-2.0 V; ENABLEx = LOW | 6 |+| Output LOW Voltage | VOL | | | 0.35 | V | VDD=3.135-3.465 V; VDDO=1.6-2.0 V; Note 4: parallel terminated 50 ohm to VDDO/2 | 6 |+| IDD Core Quiescent Power Supply Current | IDD | | | 8 | mA | VDD=2.375-2.625 V; VDDO=1.6-2.0 V; ENABLEx = LOW | 6 |+| Input HIGH Voltage ENABLEx, XTAL_IN/CLK | VIH | 1.7 | | | V | VDD=2.375-2.625 V; VDDO=1.6-2.0 V (max printed as VDD + 0.3 V) | 6 |+| Input LOW Voltage ENABLEx, XTAL_IN/CLK | VIL | -0.3 | | 0.7 | V | VDD=2.375-2.625 V; VDDO=1.6-2.0 V | 6 |+| Fmax Input Frequency Crystal | Fmax | 3 | | 40 | MHz | VDD=VDDO=3.135-3.465 V; Note 5 | 7 |+| Duty Cycle Skew | tSKEWDC | 48 | | 52 | % | VDD=VDDO=3.135-3.465 V; see Figure 4 | 7 |+| Output to Output Skew Within A Device | tSKEWO-O | 0 | 50 | 80 | ps | VDD=VDDO=3.135-3.465 V; same conditions | 7 |+| Output rise and fall times (20%; 80%) | tr/tf | 200 | | 800 | ps | VDD=VDDO=3.135-3.465 V | 7 |+| Duty Cycle Skew | tSKEWDC | 47 | | 53 | % | VDD=VDDO=2.375-2.625 V; see Figure 4 | 7 |+| Output rise and fall times (20%; 80%) | tr/tf | 200 | | 900 | ps | VDD=VDDO=1.6-2.0 V | 7 |+| Frequency, Fundamental AT-cut crystal | | 10 | | 40 | MHz | Recommended crystal parameter | 3 |+| Load Capacitance | | 16 | | 20 | pF | Recommended crystal parameter; see Application Information for CL loading | 3 |+| Shunt Capacitance | C0 | | | 7 | pF | Recommended crystal parameter | 3 |+| Equivalent Series Resistance | ESR | | | 50 | ohm | Recommended crystal parameter | 3 |+| Drive Level | | | | 1 | mW | Recommended crystal parameter | 3 |+| Thermal Resistance (Junction-to-Ambient), QFN-20, 0 lfpm | θJA | | 47 | | °C/W | 0 lfpm | 4 |+| Thermal Resistance (Junction-to-Ambient), QFN-20, 500 lfpm | θJA | | 33 | | °C/W | 500 lfpm | 4 |+| Thermal Resistance (Junction-to-Case), QFN-20 | θJC | | 18 | | °C/W | Note 3: JEDEC 2S2P multilayer board | 4 |++## CAD (KiCad official)++- Symbol: `NB3H83905CMNG`+- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`+- 3D model: QFN-20(4x4) (KiCad packages3D, STEP)+- 3D model files: `nb3h83905cmng-etched.step` / `nb3h83905cmng-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nb3h83905cmng.step` / `nb3h83905cmng.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/nb3h83905cmn-d.pdf) (15 pp, sha256 `3bf0459629f27493`, retrieved 2026-10-30, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/nb3h83905cmng-datasheet.pdf)
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