component
MSPM0G3506SRGZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# MSPM0G3506SRGZR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)++MSPM0G3506SRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PA0 | bidirectional | 5 V-tolerant open-drain GPIO (alternates UART0_TX, I2C0_SDA, TIMA0_C0, FCC_IN) that can wake the device from SHUTDOWN and needs an external pull-up to output high. |+| 2 | PA1 | bidirectional | 5 V-tolerant open-drain GPIO (alternates UART0_RX, I2C0_SCL, TIMA0_C1, TIMG8_C0) that can wake the device from SHUTDOWN and needs an external pull-up to output high. |+| 3 | PA28 | bidirectional | High-drive GPIO (alternates UART0_TX, I2C0_SDA, TIMA0_C3, TIMG7_C0, TIMA1_C0) that can wake the device from SHUTDOWN. |+| 4 | NRST | input | Active-low reset input that must be pulled up to VDD, otherwise the device cannot start. |+| 5 | PA31 | bidirectional | High-drive GPIO (alternates UART0_RX, I2C0_SCL, CLK_OUT, TIMA1_C1) that can wake the device from SHUTDOWN. |+| 6 | VDD | power_in | Device supply input, recommended 1.62 V to 3.6 V, decoupled to VSS with 10 µF and 0.1 µF low-ESR ceramic capacitors placed within a few millimetres of the pin. |+| 7 | VSS | power_in | Ground reference for the device; TI recommends connecting the exposed thermal pad to VSS. |+| 8 | PA2 | bidirectional | Standard GPIO (alternates ROSC, SPI0_CS0, TIMG8_C1, SPI1_CS0); when the SYSOSC frequency-correction loop is used, the 100 kΩ ±0.1% ROSC resistor connects to this pin and VSS. |+| 9 | PA3 | bidirectional | Standard GPIO (alternates LFXIN 32 kHz crystal input, COMP1_OUT, SPI0_CS1, UART2_CTS). |+| 10 | PA4 | bidirectional | Standard GPIO (alternates LFXOUT 32 kHz crystal output, LFCLK_IN digital clock input, SPI0_POCI, UART2_RTS). |+| 11 | PA5 | bidirectional | Standard GPIO (alternates HFXIN high-frequency crystal input, SPI0_PICO, TIMA_FAL1, FCC_IN). |+| 12 | PA6 | bidirectional | Standard GPIO (alternates HFXOUT high-frequency crystal output, HFCLK_IN digital clock input, SPI0_SCK, TIMA_FAL0). |+| 13 | PA7 | bidirectional | Standard GPIO (alternates COMP0_OUT, CLK_OUT, TIMG8_C0, TIMA0_C2). |+| 14 | PB2 | bidirectional | Standard GPIO (alternates UART3_TX, UART2_CTS, I2C1_SCL, TIMA0_C3). |+| 15 | PB3 | bidirectional | Standard GPIO (alternates UART3_RX, UART2_RTS, I2C1_SDA, TIMA0_C3N). |+| 16 | PA8 | bidirectional | Standard GPIO (alternates UART1_TX, SPI0_CS0, UART0_RTS, TIMA0_C0). |+| 17 | PA9 | bidirectional | High-speed GPIO (alternates UART1_RX, SPI0_PICO, UART0_CTS, RTC_OUT, CLK_OUT). |+| 18 | PA10 | bidirectional | High-drive GPIO (alternates UART0_TX, SPI0_POCI, I2C0_SDA, TIMA1_C0, CLK_OUT). |+| 19 | PA11 | bidirectional | High-drive GPIO (alternates UART0_RX, SPI0_SCK, I2C0_SCL, TIMA1_C1, COMP0_OUT). |+| 20 | PB6 | bidirectional | Standard GPIO (alternates UART1_TX, SPI1_CS0, SPI0_CS1, TIMG8_C0). |+| 21 | PB7 | bidirectional | Standard GPIO (alternates UART1_RX, SPI1_POCI, SPI0_CS2, TIMG8_C1). |+| 22 | PB8 | bidirectional | Standard GPIO (alternates UART1_CTS, SPI1_PICO, TIMA0_C0, COMP1_OUT). |+| 23 | PB9 | bidirectional | Standard GPIO (alternates UART1_RTS, SPI1_SCK, TIMA0_C1, TIMA0_C0N). |+| 24 | PB14 | bidirectional | Standard GPIO (alternates SPI1_CS3, SPI1_POCI, SPI0_CS3, TIMG12_C1, TIMG8_IDX, TIMA0_C0). |+| 25 | PB15 | bidirectional | Standard GPIO (alternates UART2_TX, SPI1_PICO, UART3_CTS, TIMG8_C0, TIMG7_C0). |+| 26 | PB16 | bidirectional | Standard GPIO (alternates UART2_RX, SPI1_SCK, UART3_RTS, TIMG8_C1, TIMG7_C1). |+| 27 | PA12 | bidirectional | High-speed GPIO (alternates UART3_CTS, SPI0_SCK, TIMG0_C0, CAN_TX, TIMA0_C3, FCC_IN). |+| 28 | PA13 | bidirectional | High-speed GPIO shared with COMP0_IN2- (alternates UART3_RTS, SPI0_POCI, UART3_RX, CAN_RX, TIMA0_C3N). |+| 29 | PA14 | bidirectional | High-speed GPIO shared with ADC0 input A0_12 and COMP0_IN2+ (alternates UART0_CTS, SPI0_PICO, UART3_TX, CLK_OUT). |+| 30 | PA15 | bidirectional | Standard GPIO shared with ADC1 input A1_0, DAC_OUT, and OPA/COMP inputs; avoid external circuitry on this pin when DAC_OUT is used. |+| 31 | PA16 | bidirectional | Standard GPIO shared with ADC1 input A1_1 and OPA1_OUT (alternates COMP2_OUT, SPI1_POCI, I2C1_SDA, FCC_IN). |+| 32 | PA17 | bidirectional | Standard GPIO with wake-from-SHUTDOWN capability, shared with ADC1 input A1_2, OPA1_IN1-, and COMP0_IN1- (alternates UART1_TX, SPI1_SCK, I2C1_SCL). |+| 33 | PA18 | bidirectional | Standard GPIO with wake-from-SHUTDOWN capability, shared with ADC1 input A1_3, OPA1_IN1+, COMP0_IN1+, and GPAMP_IN- (alternates UART1_RX, SPI1_PICO, I2C1_SDA). |+| 34 | PA19 | bidirectional | High-speed GPIO whose default function is SWDIO, the bidirectional serial-wire debug data line. |+| 35 | PA20 | input | Standard GPIO whose default function is SWCLK, the serial-wire debug clock input from the debug probe. |+| 36 | PB17 | bidirectional | Standard GPIO shared with ADC1 input A1_4 and COMP1_IN2- (alternates UART2_TX, SPI0_PICO, SPI1_CS1, TIMA1_C0). |+| 37 | PB18 | bidirectional | Standard GPIO shared with ADC1 input A1_5 and COMP1_IN2+ (alternates UART2_RX, SPI0_SCK, SPI1_CS2, TIMA1_C1). |+| 38 | PB19 | bidirectional | Standard GPIO shared with ADC1 input A1_6, COMP2_IN1+, and OPA1_IN0+ (alternates COMP2_OUT, SPI0_POCI, TIMG8_C1, UART0_CTS). |+| 39 | PA21 | bidirectional | Standard GPIO shared with ADC1 input A1_7, COMP2_IN1-, and the VREF- ground/external-reference pin (alternates UART2_TX, TIMG8_C0, UART1_CTS, TIMA0_C0). |+| 40 | PA22 | bidirectional | Standard GPIO shared with ADC0 input A0_7, GPAMP_OUT, and OPA0_OUT (alternates UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1, CLK_OUT). |+| 41 | PB20 | bidirectional | Standard GPIO shared with ADC0 input A0_6 and OPA1_IN0- (alternates SPI0_CS2, SPI1_CS0, TIMA0_C2, TIMG12_C0). |+| 42 | PB24 | bidirectional | Standard GPIO shared with ADC0 input A0_5 and COMP1_IN1+ (alternates SPI0_CS3, SPI0_CS1, TIMA0_C3, TIMG12_C1). |+| 43 | PA23 | bidirectional | Standard GPIO shared with COMP1_IN1- and VREF+, the external voltage-reference input or internal reference output, which needs a decoupling capacitor to VREF-/GND when used (alternates UART2_TX, SPI0_CS3, TIMA0_C3, TIMG0_C0). |+| 44 | PA24 | bidirectional | Standard GPIO shared with ADC0 input A0_3 and OPA0_IN1- (alternates UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1). |+| 45 | PA25 | bidirectional | Standard GPIO shared with ADC0 input A0_2 and OPA0_IN1+ (alternates UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3). |+| 46 | PA26 | bidirectional | Standard GPIO shared with ADC0 input A0_1, COMP0_IN0+, OPA0_IN0+, and GPAMP_IN+ (alternates UART3_TX, SPI1_CS0, TIMG8_C0, CAN_TX). |+| 47 | PA27 | bidirectional | Standard GPIO shared with ADC0 input A0_0, COMP0_IN0-, and OPA0_IN0- (alternates RTC_OUT, SPI1_CS1, TIMG8_C1, CAN_RX). |+| 48 | VCORE | power_out | Regulated core-supply output that must only connect to a 0.47 µF capacitor to VSS placed close to the pin; no external voltage or load may be applied. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `MSPM0G3506SRGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `mspm0g3506srgzr-etched.step` / `mspm0g3506srgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mspm0g3506srgzr.step` / `mspm0g3506srgzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590920957609791488) (98 pp, sha256 `eb8a69598fc3b437`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mspm0g3506srgzr-datasheet.pdf)
page.jsonadded+446@@ -0,0 +1,446 @@+{+ "slug": "mspm0g3506srgzr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "mspm0g3506srgzr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "mspm0g3506srgzr.kicad_sym",+ "mspm0g3506srgzr.kicad_mod",+ "mspm0g3506srgzr.glb",+ "mspm0g3506srgzr.step",+ "mspm0g3506srgzr.lbr",+ "docs/hero.png",+ "docs/mspm0g3506srgzr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "mspm0g3506srgzr-hero.glb",+ "mspm0g3506srgzr-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSPM0G3506SRGZR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590920957609791488",+ "parts": {+ "symbol": "mspm0g3506srgzr.kicad_sym",+ "footprint": "mspm0g3506srgzr.kicad_mod",+ "model_3d": "mspm0g3506srgzr-hero.glb",+ "model_3d_plain": "mspm0g3506srgzr.glb",+ "model_3d_step": "mspm0g3506srgzr-etched.step",+ "model_3d_step_plain": "mspm0g3506srgzr.step",+ "lbr": "mspm0g3506srgzr.lbr"+ },+ "distributor_links": {+ "lcsc": "C22362627",+ "digikey": "296-MSPM0G3506SRGZRTR-ND",+ "mouser": "595-MSPM0G3506SRGZR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T02:46:44Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-MSPM0G3506SRGZRTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-MSPM0G3506SRGZR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PA0",+ "type": "bidirectional",+ "description": "5 V-tolerant open-drain GPIO (alternates UART0_TX, I2C0_SDA, TIMA0_C0, FCC_IN) that can wake the device from SHUTDOWN and needs an external pull-up to output high."+ },+ {+ "number": "2",+ "name": "PA1",+ "type": "bidirectional",+ "description": "5 V-tolerant open-drain GPIO (alternates UART0_RX, I2C0_SCL, TIMA0_C1, TIMG8_C0) that can wake the device from SHUTDOWN and needs an external pull-up to output high."+ },+ {+ "number": "3",+ "name": "PA28",+ "type": "bidirectional",+ "description": "High-drive GPIO (alternates UART0_TX, I2C0_SDA, TIMA0_C3, TIMG7_C0, TIMA1_C0) that can wake the device from SHUTDOWN."+ },+ {+ "number": "4",+ "name": "NRST",+ "type": "input",+ "description": "Active-low reset input that must be pulled up to VDD, otherwise the device cannot start."+ },+ {+ "number": "5",+ "name": "PA31",+ "type": "bidirectional",+ "description": "High-drive GPIO (alternates UART0_RX, I2C0_SCL, CLK_OUT, TIMA1_C1) that can wake the device from SHUTDOWN."+ },+ {+ "number": "6",+ "name": "VDD",+ "type": "power_in",+ "description": "Device supply input, recommended 1.62 V to 3.6 V, decoupled to VSS with 10 µF and 0.1 µF low-ESR ceramic capacitors placed within a few millimetres of the pin."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for the device; TI recommends connecting the exposed thermal pad to VSS."+ },+ {+ "number": "8",+ "name": "PA2",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates ROSC, SPI0_CS0, TIMG8_C1, SPI1_CS0); when the SYSOSC frequency-correction loop is used, the 100 kΩ ±0.1% ROSC resistor connects to this pin and VSS."+ },+ {+ "number": "9",+ "name": "PA3",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates LFXIN 32 kHz crystal input, COMP1_OUT, SPI0_CS1, UART2_CTS)."+ },+ {+ "number": "10",+ "name": "PA4",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates LFXOUT 32 kHz crystal output, LFCLK_IN digital clock input, SPI0_POCI, UART2_RTS)."+ },+ {+ "number": "11",+ "name": "PA5",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates HFXIN high-frequency crystal input, SPI0_PICO, TIMA_FAL1, FCC_IN)."+ },+ {+ "number": "12",+ "name": "PA6",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates HFXOUT high-frequency crystal output, HFCLK_IN digital clock input, SPI0_SCK, TIMA_FAL0)."+ },+ {+ "number": "13",+ "name": "PA7",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates COMP0_OUT, CLK_OUT, TIMG8_C0, TIMA0_C2)."+ },+ {+ "number": "14",+ "name": "PB2",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART3_TX, UART2_CTS, I2C1_SCL, TIMA0_C3)."+ },+ {+ "number": "15",+ "name": "PB3",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART3_RX, UART2_RTS, I2C1_SDA, TIMA0_C3N)."+ },+ {+ "number": "16",+ "name": "PA8",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART1_TX, SPI0_CS0, UART0_RTS, TIMA0_C0)."+ },+ {+ "number": "17",+ "name": "PA9",+ "type": "bidirectional",+ "description": "High-speed GPIO (alternates UART1_RX, SPI0_PICO, UART0_CTS, RTC_OUT, CLK_OUT)."+ },+ {+ "number": "18",+ "name": "PA10",+ "type": "bidirectional",+ "description": "High-drive GPIO (alternates UART0_TX, SPI0_POCI, I2C0_SDA, TIMA1_C0, CLK_OUT)."+ },+ {+ "number": "19",+ "name": "PA11",+ "type": "bidirectional",+ "description": "High-drive GPIO (alternates UART0_RX, SPI0_SCK, I2C0_SCL, TIMA1_C1, COMP0_OUT)."+ },+ {+ "number": "20",+ "name": "PB6",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART1_TX, SPI1_CS0, SPI0_CS1, TIMG8_C0)."+ },+ {+ "number": "21",+ "name": "PB7",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART1_RX, SPI1_POCI, SPI0_CS2, TIMG8_C1)."+ },+ {+ "number": "22",+ "name": "PB8",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART1_CTS, SPI1_PICO, TIMA0_C0, COMP1_OUT)."+ },+ {+ "number": "23",+ "name": "PB9",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART1_RTS, SPI1_SCK, TIMA0_C1, TIMA0_C0N)."+ },+ {+ "number": "24",+ "name": "PB14",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates SPI1_CS3, SPI1_POCI, SPI0_CS3, TIMG12_C1, TIMG8_IDX, TIMA0_C0)."+ },+ {+ "number": "25",+ "name": "PB15",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART2_TX, SPI1_PICO, UART3_CTS, TIMG8_C0, TIMG7_C0)."+ },+ {+ "number": "26",+ "name": "PB16",+ "type": "bidirectional",+ "description": "Standard GPIO (alternates UART2_RX, SPI1_SCK, UART3_RTS, TIMG8_C1, TIMG7_C1)."+ },+ {+ "number": "27",+ "name": "PA12",+ "type": "bidirectional",+ "description": "High-speed GPIO (alternates UART3_CTS, SPI0_SCK, TIMG0_C0, CAN_TX, TIMA0_C3, FCC_IN)."+ },+ {+ "number": "28",+ "name": "PA13",+ "type": "bidirectional",+ "description": "High-speed GPIO shared with COMP0_IN2- (alternates UART3_RTS, SPI0_POCI, UART3_RX, CAN_RX, TIMA0_C3N)."+ },+ {+ "number": "29",+ "name": "PA14",+ "type": "bidirectional",+ "description": "High-speed GPIO shared with ADC0 input A0_12 and COMP0_IN2+ (alternates UART0_CTS, SPI0_PICO, UART3_TX, CLK_OUT)."+ },+ {+ "number": "30",+ "name": "PA15",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC1 input A1_0, DAC_OUT, and OPA/COMP inputs; avoid external circuitry on this pin when DAC_OUT is used."+ },+ {+ "number": "31",+ "name": "PA16",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC1 input A1_1 and OPA1_OUT (alternates COMP2_OUT, SPI1_POCI, I2C1_SDA, FCC_IN)."+ },+ {+ "number": "32",+ "name": "PA17",+ "type": "bidirectional",+ "description": "Standard GPIO with wake-from-SHUTDOWN capability, shared with ADC1 input A1_2, OPA1_IN1-, and COMP0_IN1- (alternates UART1_TX, SPI1_SCK, I2C1_SCL)."+ },+ {+ "number": "33",+ "name": "PA18",+ "type": "bidirectional",+ "description": "Standard GPIO with wake-from-SHUTDOWN capability, shared with ADC1 input A1_3, OPA1_IN1+, COMP0_IN1+, and GPAMP_IN- (alternates UART1_RX, SPI1_PICO, I2C1_SDA)."+ },+ {+ "number": "34",+ "name": "PA19",+ "type": "bidirectional",+ "description": "High-speed GPIO whose default function is SWDIO, the bidirectional serial-wire debug data line."+ },+ {+ "number": "35",+ "name": "PA20",+ "type": "input",+ "description": "Standard GPIO whose default function is SWCLK, the serial-wire debug clock input from the debug probe."+ },+ {+ "number": "36",+ "name": "PB17",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC1 input A1_4 and COMP1_IN2- (alternates UART2_TX, SPI0_PICO, SPI1_CS1, TIMA1_C0)."+ },+ {+ "number": "37",+ "name": "PB18",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC1 input A1_5 and COMP1_IN2+ (alternates UART2_RX, SPI0_SCK, SPI1_CS2, TIMA1_C1)."+ },+ {+ "number": "38",+ "name": "PB19",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC1 input A1_6, COMP2_IN1+, and OPA1_IN0+ (alternates COMP2_OUT, SPI0_POCI, TIMG8_C1, UART0_CTS)."+ },+ {+ "number": "39",+ "name": "PA21",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC1 input A1_7, COMP2_IN1-, and the VREF- ground/external-reference pin (alternates UART2_TX, TIMG8_C0, UART1_CTS, TIMA0_C0)."+ },+ {+ "number": "40",+ "name": "PA22",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_7, GPAMP_OUT, and OPA0_OUT (alternates UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1, CLK_OUT)."+ },+ {+ "number": "41",+ "name": "PB20",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_6 and OPA1_IN0- (alternates SPI0_CS2, SPI1_CS0, TIMA0_C2, TIMG12_C0)."+ },+ {+ "number": "42",+ "name": "PB24",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_5 and COMP1_IN1+ (alternates SPI0_CS3, SPI0_CS1, TIMA0_C3, TIMG12_C1)."+ },+ {+ "number": "43",+ "name": "PA23",+ "type": "bidirectional",+ "description": "Standard GPIO shared with COMP1_IN1- and VREF+, the external voltage-reference input or internal reference output, which needs a decoupling capacitor to VREF-/GND when used (alternates UART2_TX, SPI0_CS3, TIMA0_C3, TIMG0_C0)."+ },+ {+ "number": "44",+ "name": "PA24",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_3 and OPA0_IN1- (alternates UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1)."+ },+ {+ "number": "45",+ "name": "PA25",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_2 and OPA0_IN1+ (alternates UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3)."+ },+ {+ "number": "46",+ "name": "PA26",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_1, COMP0_IN0+, OPA0_IN0+, and GPAMP_IN+ (alternates UART3_TX, SPI1_CS0, TIMG8_C0, CAN_TX)."+ },+ {+ "number": "47",+ "name": "PA27",+ "type": "bidirectional",+ "description": "Standard GPIO shared with ADC0 input A0_0, COMP0_IN0-, and OPA0_IN0- (alternates RTC_OUT, SPI1_CS1, TIMG8_C1, CAN_RX)."+ },+ {+ "number": "48",+ "name": "VCORE",+ "type": "power_out",+ "description": "Regulated core-supply output that must only connect to a 0.47 µF capacitor to VSS placed close to the pin; no external voltage or load may be applied."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad of the VQFN-48 package has no pin number in the datasheet, so it is not list; The 48-pin mapping comes from the 48 LQFP/VQFN column of Table 6-1 (pin attributes) and Table 6-3 (s; The document is marked ADVANCE INFORMATION (preliminary) and covers the whole MSPM0G3505/3506/3507 f",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 67,+ "cost_usd": 0.4331,+ "at": "2026-10-08T02:46:26"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590920957609791488",+ "pages": 98,+ "sha256": "eb8a69598fc3b437",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "mspm0g3506srgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "mspm0g3506srgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "162aa5ff1306465c7a85cc6c1200d07fb2c0540ee4bb1446a93ec1d962f7cdb4",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}