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MSP430G2744IRHA40T
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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# MSP430G2744IRHA40T++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)++MSP430G2744IRHA40T from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DVSS | power_in | Digital ground reference (VSS). |+| 2 | XOUT/P2.7 | bidirectional | Output terminal of the crystal oscillator, also general-purpose digital I/O P2.7; if used as an input, excess current flows until P2SEL.7 is cleared. |+| 3 | XIN/P2.6 | bidirectional | Input terminal of the crystal oscillator, also general-purpose digital I/O P2.6. |+| 4 | DVSS | power_in | Digital ground reference (VSS). |+| 5 | RST/NMI/SBWTDIO | input | Reset or nonmaskable interrupt input, and Spy-Bi-Wire test data input/output during programming and test. |+| 6 | P2.0/ACLK/A0 | bidirectional | General-purpose digital I/O with ACLK output and ADC10 analog input A0. |+| 7 | P2.1/TAINCLK/SMCLK/A1 | bidirectional | General-purpose digital I/O with Timer_A INCLK clock input, SMCLK output and ADC10 analog input A1. |+| 8 | P2.2/TA0/A2 | bidirectional | General-purpose digital I/O with Timer_A CCI0B capture input, TA0 compare output, BSL receive and ADC10 analog input A2. |+| 9 | P3.0/UCB0STE/UCA0CLK/A5 | bidirectional | General-purpose digital I/O with USCI_B0 slave transmit enable, USCI_A0 clock input/output and ADC10 analog input A5. |+| 10 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O with USCI_B0 slave-in/master-out in SPI mode or I2C data (SDA) in I2C mode. |+| 11 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O with USCI_B0 slave-out/master-in in SPI mode or I2C clock (SCL) in I2C mode. |+| 12 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O with USCI_B0 clock input/output and USCI_A0 slave transmit enable. |+| 13 | AVSS | power_in | Analog ground reference. |+| 14 | AVCC | power_in | Analog supply voltage (AVCC = DVCC = VCC). |+| 15 | P4.0/TB0 | bidirectional | General-purpose digital I/O with Timer_B CCI0A capture input and TB0 compare output. |+| 16 | P4.1/TB1 | bidirectional | General-purpose digital I/O with Timer_B CCI1A capture input and TB1 compare output. |+| 17 | P4.2/TB2 | bidirectional | General-purpose digital I/O with Timer_B CCI2A capture input and TB2 compare output. |+| 18 | P4.3/TB0/A12 | bidirectional | General-purpose digital I/O with Timer_B CCI0B capture input, TB0 compare output and ADC10 analog input A12. |+| 19 | P4.4/TB1/A13 | bidirectional | General-purpose digital I/O with Timer_B CCI1B capture input, TB1 compare output and ADC10 analog input A13. |+| 20 | P4.5/TB2/A14 | bidirectional | General-purpose digital I/O with Timer_B TB2 compare output and ADC10 analog input A14. |+| 21 | P4.6/TBOUTH/A15 | bidirectional | General-purpose digital I/O; Timer_B TBOUTH switches all TB0 to TB3 outputs to high impedance; ADC10 analog input A15. |+| 22 | P4.7/TBCLK | bidirectional | General-purpose digital I/O with Timer_B clock signal TBCLK input. |+| 23 | P3.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O with USCI_A0 transmit data output in UART mode or slave-in/master-out in SPI mode. |+| 24 | P3.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O with USCI_A0 receive data input in UART mode or slave-out/master-in in SPI mode. |+| 25 | P3.6/A6 | bidirectional | General-purpose digital I/O with ADC10 analog input A6. |+| 26 | P3.7/A7 | bidirectional | General-purpose digital I/O with ADC10 analog input A7. |+| 27 | P2.3/TA1/A3/VREF-/VeREF- | bidirectional | General-purpose digital I/O with Timer_A CCI1B capture input, TA1 compare output, ADC10 analog input A3, and negative reference voltage output/input. |+| 28 | P2.4/TA2/A4/VREF+/VeREF+ | bidirectional | General-purpose digital I/O with Timer_A TA2 compare output, ADC10 analog input A4, and positive reference voltage output/input. |+| 29 | P1.0/TACLK/ADC10CLK | bidirectional | General-purpose digital I/O with Timer_A TACLK clock signal input and ADC10 conversion clock. |+| 30 | P1.1/TA0 | bidirectional | General-purpose digital I/O with Timer_A CCI0A capture input, TA0 compare output, and BSL transmit. |+| 31 | P1.2/TA1 | bidirectional | General-purpose digital I/O with Timer_A CCI1A capture input and TA1 compare output. |+| 32 | P1.3/TA2 | bidirectional | General-purpose digital I/O with Timer_A CCI2A capture input and TA2 compare output. |+| 33 | P1.4/SMCLK/TCK | bidirectional | General-purpose digital I/O with SMCLK signal output and JTAG test clock input for device programming and test. |+| 34 | P1.5/TA0/TMS | bidirectional | General-purpose digital I/O with Timer_A TA0 compare output and JTAG test mode select input for device programming and test. |+| 35 | P1.6/TA1/TDI/TCLK | bidirectional | General-purpose digital I/O with Timer_A TA1 compare output and JTAG test data input or test clock input for programming and test. |+| 36 | P1.7/TA2/TDO/TDI | bidirectional | General-purpose digital I/O with Timer_A TA2 compare output and JTAG test data output or test data input for programming and test (TDO or TDI selected via JTAG instruction). |+| 37 | TEST/SBWTCK | input | Selects test mode for JTAG pins on Port 1, the device protection fuse is connected to TEST, and it serves as Spy-Bi-Wire test clock input during programming and test. |+| 38 | DVCC | power_in | Digital supply voltage; 1.8 V to 3.6 V during program execution and 2.2 V to 3.6 V during flash program and erase. |+| 39 | DVCC | power_in | Digital supply voltage; 1.8 V to 3.6 V during program execution and 2.2 V to 3.6 V during flash program and erase. |+| 40 | P2.5/ROSC | bidirectional | General-purpose digital I/O and input for an external DCO resistor that defines the DCO frequency. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Embedded Processors & Controllers |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `MSP430G2744IRHA40T`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `msp430g2744irha40t-etched.step` / `msp430g2744irha40t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430g2744irha40t.step` / `msp430g2744irha40t.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430g2744) (94 pp, sha256 `e255f144b1f27e02`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430g2744irha40t-datasheet.pdf)
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if used as an input, excess current flows until P2SEL.7 is cleared."+ },+ {+ "number": "3",+ "name": "XIN/P2.6",+ "type": "bidirectional",+ "description": "Input terminal of the crystal oscillator, also general-purpose digital I/O P2.6."+ },+ {+ "number": "4",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground reference (VSS)."+ },+ {+ "number": "5",+ "name": "RST/NMI/SBWTDIO",+ "type": "input",+ "description": "Reset or nonmaskable interrupt input, and Spy-Bi-Wire test data input/output during programming and test."+ },+ {+ "number": "6",+ "name": "P2.0/ACLK/A0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with ACLK output and ADC10 analog input A0."+ },+ {+ "number": "7",+ "name": "P2.1/TAINCLK/SMCLK/A1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A INCLK clock input, SMCLK output and ADC10 analog input A1."+ },+ {+ "number": "8",+ "name": "P2.2/TA0/A2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A CCI0B capture input, TA0 compare output, BSL receive and ADC10 analog input A2."+ },+ {+ "number": "9",+ "name": "P3.0/UCB0STE/UCA0CLK/A5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with USCI_B0 slave transmit enable, USCI_A0 clock input/output and ADC10 analog input A5."+ },+ {+ "number": "10",+ "name": "P3.1/UCB0SIMO/UCB0SDA",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with USCI_B0 slave-in/master-out in SPI mode or I2C data (SDA) in I2C mode."+ },+ {+ "number": "11",+ "name": "P3.2/UCB0SOMI/UCB0SCL",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with USCI_B0 slave-out/master-in in SPI mode or I2C clock (SCL) in I2C mode."+ },+ {+ "number": "12",+ "name": "P3.3/UCB0CLK/UCA0STE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with USCI_B0 clock input/output and USCI_A0 slave transmit enable."+ },+ {+ "number": "13",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground reference."+ },+ {+ "number": "14",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog supply voltage (AVCC = DVCC = VCC)."+ },+ {+ "number": "15",+ "name": "P4.0/TB0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B CCI0A capture input and TB0 compare output."+ },+ {+ "number": "16",+ "name": "P4.1/TB1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B CCI1A capture input and TB1 compare output."+ },+ {+ "number": "17",+ "name": "P4.2/TB2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B CCI2A capture input and TB2 compare output."+ },+ {+ "number": "18",+ "name": "P4.3/TB0/A12",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B CCI0B capture input, TB0 compare output and ADC10 analog input A12."+ },+ {+ "number": "19",+ "name": "P4.4/TB1/A13",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B CCI1B capture input, TB1 compare output and ADC10 analog input A13."+ },+ {+ "number": "20",+ "name": "P4.5/TB2/A14",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B TB2 compare output and ADC10 analog input A14."+ },+ {+ "number": "21",+ "name": "P4.6/TBOUTH/A15",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; Timer_B TBOUTH switches all TB0 to TB3 outputs to high impedance; ADC10 analog input A15."+ },+ {+ "number": "22",+ "name": "P4.7/TBCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_B clock signal TBCLK input."+ },+ {+ "number": "23",+ "name": "P3.4/UCA0TXD/UCA0SIMO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with USCI_A0 transmit data output in UART mode or slave-in/master-out in SPI mode."+ },+ {+ "number": "24",+ "name": "P3.5/UCA0RXD/UCA0SOMI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with USCI_A0 receive data input in UART mode or slave-out/master-in in SPI mode."+ },+ {+ "number": "25",+ "name": "P3.6/A6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with ADC10 analog input A6."+ },+ {+ "number": "26",+ "name": "P3.7/A7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with ADC10 analog input A7."+ },+ {+ "number": "27",+ "name": "P2.3/TA1/A3/VREF-/VeREF-",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A CCI1B capture input, TA1 compare output, ADC10 analog input A3, and negative reference voltage output/input."+ },+ {+ "number": "28",+ "name": "P2.4/TA2/A4/VREF+/VeREF+",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A TA2 compare output, ADC10 analog input A4, and positive reference voltage output/input."+ },+ {+ "number": "29",+ "name": "P1.0/TACLK/ADC10CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A TACLK clock signal input and ADC10 conversion clock."+ },+ {+ "number": "30",+ "name": "P1.1/TA0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A CCI0A capture input, TA0 compare output, and BSL transmit."+ },+ {+ "number": "31",+ "name": "P1.2/TA1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A CCI1A capture input and TA1 compare output."+ },+ {+ "number": "32",+ "name": "P1.3/TA2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A CCI2A capture input and TA2 compare output."+ },+ {+ "number": "33",+ "name": "P1.4/SMCLK/TCK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with SMCLK signal output and JTAG test clock input for device programming and test."+ },+ {+ "number": "34",+ "name": "P1.5/TA0/TMS",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A TA0 compare output and JTAG test mode select input for device programming and test."+ },+ {+ "number": "35",+ "name": "P1.6/TA1/TDI/TCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A TA1 compare output and JTAG test data input or test clock input for programming and test."+ },+ {+ "number": "36",+ "name": "P1.7/TA2/TDO/TDI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with Timer_A TA2 compare output and JTAG test data output or test data input for programming and test (TDO or TDI selected via JTAG instruction)."+ },+ {+ "number": "37",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Selects test mode for JTAG pins on Port 1, the device protection fuse is connected to TEST, and it serves as Spy-Bi-Wire test clock input during programming and test."+ },+ {+ "number": "38",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital supply voltage; 1.8 V to 3.6 V during program execution and 2.2 V to 3.6 V during flash program and erase."+ },+ {+ "number": "39",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital supply voltage; 1.8 V to 3.6 V during program execution and 2.2 V to 3.6 V during flash program and erase."+ },+ {+ "number": "40",+ "name": "P2.5/ROSC",+ "type": "bidirectional",+ "description": "General-purpose digital I/O and input for an external DCO resistor that defines the DCO frequency."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The QFN exposed thermal pad (listed as 'QFN Pad', NA in Table 4-1) has no numbered terminal, so it i; Pin mapping was taken from the RHA column of Table 4-1 (pages 10-12) because the text extraction of ; Table 4-1 names pin 20 as P4.5/TB2/A14, while the port P4.5 schematic (Section 6.19.16) labels it P4",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 41,+ "cost_usd": 0.1929,+ "at": "2026-10-08T19:17:45"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430g2744",+ "pages": 94,+ "sha256": "e255f144b1f27e02",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430g2744irha40t.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430g2744irha40t-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "45c54617f670d15d374f0e7aad4d4117ef35387088bd02ace473f3d7d743d1c5",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}