MSP430FR5858IRHAR

@@ -0,0 +1,88 @@+# MSP430FR5858IRHAR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-40(6x6)++MSP430FR5858IRHAR from Texas Instruments, in a VQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose digital I/O (Port 1 bit 0) with port interrupt and wake-up from LPMx.5. Muxed with Timer_A0 CCR1 (CCI1A capture / Out1 compare), external DMA trigger DMAE0, RTC clock calibration output RTCCLK, ADC analog input A0, comparator input C0, negative reference voltage output VREF- and external negative reference input VeREF-. |+| 2 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose digital I/O (Port 1 bit 1) with port interrupt and wake-up from LPMx.5. Muxed with Timer_A0 CCR2 (CCI2A capture / Out2 compare), Timer_A1 external clock input TA1CLK, comparator output COUT, ADC analog input A1, comparator input C1, positive reference voltage output VREF+ and external positive reference input VeREF+. |+| 3 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose digital I/O (Port 1 bit 2) with port interrupt and wake-up from LPMx.5. Muxed with Timer_A1 CCR1 (CCI1A capture / Out1), Timer_A0 external clock input TA0CLK, comparator output COUT, ADC analog input A2 and comparator input C2. |+| 4 | P3.0/A12/C12 | bidirectional | General-purpose digital I/O (Port 3 bit 0) with port interrupt and wake-up from LPMx.5. Muxed with ADC analog input A12 and comparator input C12. |+| 5 | P3.1/A13/C13 | bidirectional | General-purpose digital I/O (Port 3 bit 1) with port interrupt and wake-up from LPMx.5. Muxed with ADC analog input A13 and comparator input C13. |+| 6 | P3.2/A14/C14 | bidirectional | General-purpose digital I/O (Port 3 bit 2) with port interrupt and wake-up from LPMx.5. Muxed with ADC analog input A14 and comparator input C14. |+| 7 | P3.3/A15/C15 | bidirectional | General-purpose digital I/O (Port 3 bit 3) with port interrupt and wake-up from LPMx.5. Muxed with ADC analog input A15 and comparator input C15. |+| 8 | P1.3/TA1.2/UCB0STE/A3/C3 | bidirectional | General-purpose digital I/O (Port 1 bit 3) with port interrupt and wake-up from LPMx.5. Muxed with Timer_A1 CCR2 (CCI2A capture / Out2 compare), eUSCI_B0 SPI slave transmit enable UCB0STE, ADC analog input A3 and comparator input C3. |+| 9 | P1.4/TB0.1/UCA0STE/A4/C4 | bidirectional | General-purpose digital I/O (Port 1 bit 4) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR1 (CCI1A capture / Out1 compare), eUSCI_A0 SPI slave transmit enable UCA0STE, ADC analog input A4 and comparator input C4. |+| 10 | P1.5/TB0.2/UCA0CLK/A5/C5 | bidirectional | General-purpose digital I/O (Port 1 bit 5) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR2 (CCI2A capture / Out2 compare), eUSCI_A0 SPI clock UCA0CLK (input in slave, output in master), ADC analog input A5 and comparator input C5. |+| 11 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 | bidirectional | General-purpose digital I/O (Port J bit 0). Muxed with JTAG Test Data Output TDO, Timer_B0 high-impedance output switch TB0OUTH, SMCLK clock output, low-power debug CPU status bit SCG1 and comparator input C6. |+| 12 | PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 | bidirectional | General-purpose digital I/O (Port J bit 1). Muxed with JTAG Test Data Input TDI, JTAG test clock TCLK, MCLK output, low-power debug CPU status bit SCG0 and comparator input C7. |+| 13 | PJ.2/TMS/ACLK/SROSCOFF/C8 | bidirectional | General-purpose digital I/O (Port J bit 2). Muxed with JTAG Test Mode Select TMS, ACLK output, low-power debug CPU status bit OSCOFF and comparator input C8. |+| 14 | PJ.3/TCK/SRCPUOFF/C9 | bidirectional | General-purpose digital I/O (Port J bit 3). Muxed with JTAG Test Clock TCK, low-power debug CPU status bit CPUOFF and comparator input C9. |+| 15 | P4.0/A8 | bidirectional | General-purpose digital I/O (Port 4 bit 0) with port interrupt and wake-up from LPMx.5. Muxed with ADC analog input A8. |+| 16 | P4.1/A9 | bidirectional | General-purpose digital I/O (Port 4 bit 1) with port interrupt and wake-up from LPMx.5. Muxed with ADC analog input A9. |+| 17 | P2.5/TB0.0/UCA1TXD/UCA1SIMO | bidirectional | General-purpose digital I/O (Port 2 bit 5) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR0 (CCI0B capture / Out0 compare), eUSCI_A1 UART transmit UCA1TXD, and eUSCI_A1 SPI slave-in/master-out UCA1SIMO. |+| 18 | P2.6/TB0.1/UCA1RXD/UCA1SOMI | bidirectional | General-purpose digital I/O (Port 2 bit 6) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR1 Out1 compare, eUSCI_A1 UART receive UCA1RXD, and eUSCI_A1 SPI slave-out/master-in UCA1SOMI. |+| 19 | TEST/SBWTCK | input | Test mode select pin - enables digital I/O on JTAG pins when high. Also serves as Spy-Bi-Wire input clock (SBWTCK). Has an internal pulldown enabled and should be left open when unused. |+| 20 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input, non-maskable interrupt input, and Spy-Bi-Wire bidirectional data (SBWTDIO). Requires a 47-kΩ (or internal) pull-up and a 2.2-nF pull-down cap for SBW/JTAG compatibility. |+| 21 | P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | bidirectional | General-purpose digital I/O (Port 2 bit 0) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR6 (CCI6B capture / Out6 compare), eUSCI_A0 UART TX UCA0TXD (also UART BSL TX), eUSCI_A0 SPI slave-in/master-out UCA0SIMO, Timer_B0 clock input TB0CLK and ACLK output. |+| 22 | P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 | bidirectional | General-purpose digital I/O (Port 2 bit 1) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR0 (CCI0A capture / Out0 compare), eUSCI_A0 UART RX UCA0RXD (also UART BSL RX), and eUSCI_A0 SPI slave-out/master-in UCA0SOMI. |+| 23 | P2.2/TB0.2/UCB0CLK | bidirectional | General-purpose digital I/O (Port 2 bit 2) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR2 Out2 compare and eUSCI_B0 SPI clock UCB0CLK (input in slave, output in master). |+| 24 | P3.4/TB0.3/SMCLK | bidirectional | General-purpose digital I/O (Port 3 bit 4) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR3 (CCI3A capture / Out3 compare) and SMCLK output. |+| 25 | P3.5/TB0.4/COUT | bidirectional | General-purpose digital I/O (Port 3 bit 5) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR4 (CCI4A capture / Out4 compare) and comparator output COUT. |+| 26 | P3.6/TB0.5 | bidirectional | General-purpose digital I/O (Port 3 bit 6) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR5 (CCI5A capture / Out5 compare). |+| 27 | P3.7/TB0.6 | bidirectional | General-purpose digital I/O (Port 3 bit 7) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR6 (CCI6A capture / Out6 compare). |+| 28 | P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 | bidirectional | General-purpose digital I/O (Port 1 bit 6) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR3 (CCI3B capture / Out3 compare), eUSCI_B0 SPI slave-in/master-out UCB0SIMO, eUSCI_B0 I2C data UCB0SDA (also I2C BSL data), and Timer_A0 CCR0 (CCI0A capture / Out0 compare). |+| 29 | P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 | bidirectional | General-purpose digital I/O (Port 1 bit 7) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR4 (CCI4B capture / Out4 compare), eUSCI_B0 SPI slave-out/master-in UCB0SOMI, eUSCI_B0 I2C clock UCB0SCL (also I2C BSL clock), and Timer_A1 CCR0 (CCI0A capture / Out0 compare). |+| 30 | P4.4/TB0.5 | bidirectional | General-purpose digital I/O (Port 4 bit 4) with port interrupt and wake-up from LPMx.5. Muxed with Timer_B0 CCR5 (CCI5B capture / Out5 compare). |+| 31 | DVSS | power_in | Digital ground supply return (0 V). Tie to the board VSS plane; TI recommends powering DVSS/AVSS from the same ground reference. |+| 32 | DVCC | power_in | Digital power supply, 1.8 V to 3.6 V. TI recommends powering AVCC and DVCC from the same source; the difference between AVCC and DVCC must not exceed ±0.3 V. Decouple with a ≥1 µF low-ESR capacitor (±20%) placed close to the pin. |+| 33 | P2.7 | bidirectional | General-purpose digital I/O (Port 2 bit 7) with port interrupt and wake-up from LPMx.5. No alternate peripheral function on this package. |+| 34 | P2.3/TA0.0/UCA1STE/A6/C10 | bidirectional | General-purpose digital I/O (Port 2 bit 3) with port interrupt and wake-up from LPMx.5. Muxed with Timer_A0 CCR0 (CCI0B capture / Out0 compare), eUSCI_A1 SPI slave transmit enable UCA1STE, ADC analog input A6 and comparator input C10. |+| 35 | P2.4/TA1.0/UCA1CLK/A7/C11 | bidirectional | General-purpose digital I/O (Port 2 bit 4) with port interrupt and wake-up from LPMx.5. Muxed with Timer_A1 CCR0 (CCI0B capture / Out0 compare), eUSCI_A1 SPI clock UCA1CLK (input in slave, output in master), ADC analog input A7 and comparator input C11. |+| 36 | AVSS | power_in | Analog ground supply return (0 V). Tie to the board VSS plane together with DVSS. |+| 37 | PJ.6/HFXIN | bidirectional | General-purpose digital I/O (Port J bit 6). On the RHA package of MSP430FR585x devices this pin also serves as the input for the high-frequency crystal oscillator (HFXT). Connect a high-frequency crystal between HFXIN and HFXOUT (with appropriate load capacitors) when using HFXT. |+| 38 | PJ.7/HFXOUT | bidirectional | General-purpose digital I/O (Port J bit 7). On the RHA package of MSP430FR585x devices this pin also serves as the output for the high-frequency crystal oscillator (HFXT). |+| 39 | AVSS | power_in | Analog ground supply return (0 V). Second AVSS pin - tie to the board VSS plane along with the other AVSS/DVSS pins. |+| 40 | AVCC | power_in | Analog power supply, 1.8 V to 3.6 V. Must be within ±0.3 V of DVCC; TI recommends powering AVCC and DVCC from the same source. Decouple close to the pin. |+| PAD | EP | power_in | Exposed QFN thermal pad on the underside of the package. Texas Instruments recommends connecting the pad to VSS (0 V) for optimal thermal and electrical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40(6x6) |+| Category | Embedded Processors & Controllers |+| Pins | 41 |++## Ordering variants++Same part, different packaging or reel option.++- `MSP430FR5858IRHAR`+- `MSP430FR5858IRHAT`+- `MSP430FR5858IRHARIRGZR`+- `MSP430FR5858IRHARIRGZT`+- `MSP430FR5858IRHARIDA`+- `MSP430FR5858IRHARIDAR`++## CAD (KiCad official)++- Symbol: `MSP430FR5858IRHAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40(6x6) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr5858) (None pp, sha256 `0c77a4839a0e965e`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fr5858irhar-datasheet.pdf)