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MSP430FR2475TRHAR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# MSP430FR2475TRHAR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)++MSP430FR2475TRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DVCC | power_in | Main supply input for the digital and I/O modules, specified at 1.8 V to 3.6 V with a 4.7 µF to 10 µF capacitor recommended at DVCC. |+| 2 | RST/NMI/SBWTDIO | bidirectional | Reset input with pullup enabled after BOR, NMI input, or Spy-Bi-Wire data I/O; unused pin should use a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown. |+| 3 | TEST/SBWTCK | input | Test mode pin that selects the JTAG pin functions, with Spy-Bi-Wire clock SBWTCK input; an internal pulldown is always enabled, so leave it open if unused. |+| 4 | P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ | bidirectional | General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 TXD/SIMO, Timer TA1.2, JTAG TCK, ADC input A4 and VREF+ output; TI recommends disabling the pin interrupt during JTAG debug. |+| 5 | P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 | bidirectional | General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 RXD/SOMI, Timer TA1.1, JTAG TMS and ADC input A5. |+| 6 | P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 | bidirectional | General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 clock, Timer TA1CLK, JTAG TDI/TCLK and ADC input A6. |+| 7 | P1.7/UCA0STE/SMCLK/TDO/A7 | bidirectional | General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7. |+| 8 | P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8 | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_B1 SOMI/SCL, Timer_B TB0.5 and ADC input A8; this pin has no RHA-package remap to other ports. |+| 9 | P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9 | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_B1 SIMO/SDA, Timer_B TB0.6 and ADC input A9. |+| 10 | P1.0/UCB0STE/TA0CLK/A0/Veref+ | bidirectional | General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 STE, Timer TA0CLK, ADC input A0 and ADC positive reference Veref+. |+| 11 | P1.1/UCB0CLK/TA0.1/COMP0.0/A1 | bidirectional | General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 clock, Timer TA0.1, eCOMP0 input channel C0 and ADC input A1. |+| 12 | P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- | bidirectional | General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 SIMO/SDA, Timer TA0.2, ADC input A2 and ADC negative reference Veref-. |+| 13 | P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 | bidirectional | General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 SOMI/SCL, MCLK output and ADC input A3. |+| 14 | P2.2/ACLK/COMP0.1 | bidirectional | General-purpose I/O, also ACLK output and eCOMP0 input channel C1. |+| 15 | P4.5/UCB0SOMI/UCB0SCL/TA3.2 | bidirectional | General-purpose I/O, also eUSCI_B0 SOMI/SCL and Timer TA3.2 in its remapped (TAxRMP) position for this package. |+| 16 | P4.6/UCB0SIMO/UCB0SDA/TA3.1 | bidirectional | General-purpose I/O, also eUSCI_B0 SIMO/SDA and Timer TA3.1 in its remapped (TAxRMP) position for this package. |+| 17 | P3.0/TA2.2 | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA2.2 CCR2 capture/compare output. |+| 18 | P3.3/TA2.1 | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA2.1 CCR1 capture/compare output. |+| 19 | P2.3/TA2.0 | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA2.0 CCR0 capture/compare output. |+| 20 | P3.4/TA2CLK/COMP0OUT | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA2CLK input and eCOMP0 output COUT. |+| 21 | P3.1/UCA1STE | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_A1 STE function. |+| 22 | P2.4/UCA1CLK | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_A1 clock function. |+| 23 | P2.5/UCA1RXD/UCA1SOMI | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_A1 receive / SOMI function. |+| 24 | P2.6/UCA1TXD/UCA1SIMO | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_A1 transmit / SIMO function. |+| 25 | DNC | unconnected | Do not connect; leave this pin unconnected on the board. |+| 26 | P3.7/TA3.2 | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA3.2 CCR2 capture/compare output. |+| 27 | P4.0/TA3.1 | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA3.1 CCR1 capture/compare output. |+| 28 | P4.1/TA3.0 | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA3.0 CCR0 capture/compare output. |+| 29 | P4.2/TA3CLK | bidirectional | General-purpose I/O (reset state high-impedance), also Timer TA3CLK clock input. |+| 30 | P2.7/UCB1STE | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_B1 STE function. |+| 31 | P3.5/UCB1CLK/TB0TRG | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_B1 clock and Timer_B external trigger input TB0TRG. |+| 32 | P3.2/UCB1SIMO/UCB1SDA | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_B1 SIMO/SDA function. |+| 33 | P3.6/UCB1SOMI/UCB1SCL | bidirectional | General-purpose I/O (reset state high-impedance) with eUSCI_B1 SOMI/SCL function. |+| 34 | P4.7/UCA0STE/TB0.1 | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_A0 STE and Timer_B TB0.1 output. |+| 35 | P5.0/UCA0CLK/TB0.2 | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_A0 clock and Timer_B TB0.2 output. |+| 36 | P5.1/UCA0RXD/UCA0SOMI/TB0.3 | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_A0 RXD/SOMI and Timer_B TB0.3 output. |+| 37 | P5.2/UCA0TXD/UCA0SIMO/TB0.4 | bidirectional | General-purpose I/O (reset state high-impedance), also eUSCI_A0 TXD/SIMO and Timer_B TB0.4 output. |+| 38 | P2.0/XOUT | bidirectional | General-purpose I/O (reset state high-impedance), or XOUT output of the 32-kHz crystal oscillator. |+| 39 | P2.1/XIN | bidirectional | General-purpose I/O (reset state high-impedance), or XIN input of the 32-kHz crystal oscillator; the device supports only a 32-kHz crystal or digital clock input in XT1BYPASS mode. |+| 40 | DVSS | power_in | Ground reference for DVCC and the digital and analog modules; connect to system ground. |+| 41 | VQFN pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Embedded Processors & Controllers |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `MSP430FR2475TRHAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `msp430fr2475trhar-etched.step` / `msp430fr2475trhar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr2475trhar.step` / `msp430fr2475trhar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr2476) (119 pp, sha256 `c5ddbe428514a331`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fr2475trhar-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430fr2475trhar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430fr2475trhar.kicad_sym",+ "msp430fr2475trhar.kicad_mod",+ "msp430fr2475trhar.glb",+ "msp430fr2475trhar.step",+ "msp430fr2475trhar.lbr",+ "docs/hero.png",+ "docs/msp430fr2475trhar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430fr2475trhar-hero.glb",+ "msp430fr2475trhar-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430FR2475TRHAR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr2476",+ "parts": {+ "symbol": "msp430fr2475trhar.kicad_sym",+ "footprint": "msp430fr2475trhar.kicad_mod",+ "model_3d": "msp430fr2475trhar-hero.glb",+ "model_3d_plain": "msp430fr2475trhar.glb",+ "model_3d_step": "msp430fr2475trhar-etched.step",+ "model_3d_step_plain": "msp430fr2475trhar.step",+ "lbr": "msp430fr2475trhar.lbr"+ },+ "distributor_links": {+ "lcsc": "C2053433",+ "digikey": "296-MSP430FR2475TRHARTR-ND",+ "mouser": "595-SP430FR2475TRHAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T23:09:45Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-MSP430FR2475TRHARTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SP430FR2475TRHAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DVCC",+ "type": "power_in",+ "description": "Main supply input for the digital and I/O modules, specified at 1.8 V to 3.6 V with a 4.7 µF to 10 µF capacitor recommended at DVCC."+ },+ {+ "number": "2",+ "name": "RST/NMI/SBWTDIO",+ "type": "bidirectional",+ "description": "Reset input with pullup enabled after BOR, NMI input, or Spy-Bi-Wire data I/O; unused pin should use a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown."+ },+ {+ "number": "3",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that selects the JTAG pin functions, with Spy-Bi-Wire clock SBWTCK input; an internal pulldown is always enabled, so leave it open if unused."+ },+ {+ "number": "4",+ "name": "P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 TXD/SIMO, Timer TA1.2, JTAG TCK, ADC input A4 and VREF+ output; TI recommends disabling the pin interrupt during JTAG debug."+ },+ {+ "number": "5",+ "name": "P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 RXD/SOMI, Timer TA1.1, JTAG TMS and ADC input A5."+ },+ {+ "number": "6",+ "name": "P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 clock, Timer TA1CLK, JTAG TDI/TCLK and ADC input A6."+ },+ {+ "number": "7",+ "name": "P1.7/UCA0STE/SMCLK/TDO/A7",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with port interrupt and LPMx.5 wake-up, also eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7."+ },+ {+ "number": "8",+ "name": "P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_B1 SOMI/SCL, Timer_B TB0.5 and ADC input A8; this pin has no RHA-package remap to other ports."+ },+ {+ "number": "9",+ "name": "P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_B1 SIMO/SDA, Timer_B TB0.6 and ADC input A9."+ },+ {+ "number": "10",+ "name": "P1.0/UCB0STE/TA0CLK/A0/Veref+",+ "type": "bidirectional",+ "description": "General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 STE, Timer TA0CLK, ADC input A0 and ADC positive reference Veref+."+ },+ {+ "number": "11",+ "name": "P1.1/UCB0CLK/TA0.1/COMP0.0/A1",+ "type": "bidirectional",+ "description": "General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 clock, Timer TA0.1, eCOMP0 input channel C0 and ADC input A1."+ },+ {+ "number": "12",+ "name": "P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-",+ "type": "bidirectional",+ "description": "General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 SIMO/SDA, Timer TA0.2, ADC input A2 and ADC negative reference Veref-."+ },+ {+ "number": "13",+ "name": "P1.3/UCB0SOMI/UCB0SCL/MCLK/A3",+ "type": "bidirectional",+ "description": "General-purpose I/O with port interrupt and LPMx.5 wake-up, also eUSCI_B0 SOMI/SCL, MCLK output and ADC input A3."+ },+ {+ "number": "14",+ "name": "P2.2/ACLK/COMP0.1",+ "type": "bidirectional",+ "description": "General-purpose I/O, also ACLK output and eCOMP0 input channel C1."+ },+ {+ "number": "15",+ "name": "P4.5/UCB0SOMI/UCB0SCL/TA3.2",+ "type": "bidirectional",+ "description": "General-purpose I/O, also eUSCI_B0 SOMI/SCL and Timer TA3.2 in its remapped (TAxRMP) position for this package."+ },+ {+ "number": "16",+ "name": "P4.6/UCB0SIMO/UCB0SDA/TA3.1",+ "type": "bidirectional",+ "description": "General-purpose I/O, also eUSCI_B0 SIMO/SDA and Timer TA3.1 in its remapped (TAxRMP) position for this package."+ },+ {+ "number": "17",+ "name": "P3.0/TA2.2",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA2.2 CCR2 capture/compare output."+ },+ {+ "number": "18",+ "name": "P3.3/TA2.1",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA2.1 CCR1 capture/compare output."+ },+ {+ "number": "19",+ "name": "P2.3/TA2.0",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA2.0 CCR0 capture/compare output."+ },+ {+ "number": "20",+ "name": "P3.4/TA2CLK/COMP0OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA2CLK input and eCOMP0 output COUT."+ },+ {+ "number": "21",+ "name": "P3.1/UCA1STE",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_A1 STE function."+ },+ {+ "number": "22",+ "name": "P2.4/UCA1CLK",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_A1 clock function."+ },+ {+ "number": "23",+ "name": "P2.5/UCA1RXD/UCA1SOMI",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_A1 receive / SOMI function."+ },+ {+ "number": "24",+ "name": "P2.6/UCA1TXD/UCA1SIMO",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_A1 transmit / SIMO function."+ },+ {+ "number": "25",+ "name": "DNC",+ "type": "unconnected",+ "description": "Do not connect; leave this pin unconnected on the board."+ },+ {+ "number": "26",+ "name": "P3.7/TA3.2",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA3.2 CCR2 capture/compare output."+ },+ {+ "number": "27",+ "name": "P4.0/TA3.1",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA3.1 CCR1 capture/compare output."+ },+ {+ "number": "28",+ "name": "P4.1/TA3.0",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA3.0 CCR0 capture/compare output."+ },+ {+ "number": "29",+ "name": "P4.2/TA3CLK",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also Timer TA3CLK clock input."+ },+ {+ "number": "30",+ "name": "P2.7/UCB1STE",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_B1 STE function."+ },+ {+ "number": "31",+ "name": "P3.5/UCB1CLK/TB0TRG",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_B1 clock and Timer_B external trigger input TB0TRG."+ },+ {+ "number": "32",+ "name": "P3.2/UCB1SIMO/UCB1SDA",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_B1 SIMO/SDA function."+ },+ {+ "number": "33",+ "name": "P3.6/UCB1SOMI/UCB1SCL",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance) with eUSCI_B1 SOMI/SCL function."+ },+ {+ "number": "34",+ "name": "P4.7/UCA0STE/TB0.1",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_A0 STE and Timer_B TB0.1 output."+ },+ {+ "number": "35",+ "name": "P5.0/UCA0CLK/TB0.2",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_A0 clock and Timer_B TB0.2 output."+ },+ {+ "number": "36",+ "name": "P5.1/UCA0RXD/UCA0SOMI/TB0.3",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_A0 RXD/SOMI and Timer_B TB0.3 output."+ },+ {+ "number": "37",+ "name": "P5.2/UCA0TXD/UCA0SIMO/TB0.4",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), also eUSCI_A0 TXD/SIMO and Timer_B TB0.4 output."+ },+ {+ "number": "38",+ "name": "P2.0/XOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), or XOUT output of the 32-kHz crystal oscillator."+ },+ {+ "number": "39",+ "name": "P2.1/XIN",+ "type": "bidirectional",+ "description": "General-purpose I/O (reset state high-impedance), or XIN input of the 32-kHz crystal oscillator; the device supports only a 32-kHz crystal or digital clock input in XT1BYPASS mode."+ },+ {+ "number": "40",+ "name": "DVSS",+ "type": "power_in",+ "description": "Ground reference for DVCC and the digital and analog modules; connect to system ground."+ },+ {+ "number": "41",+ "name": "VQFN pad",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Table 7-1 page 13 (the RHA pin rows for pins 10 to 19 and the associated reset states/buffer details; Pin 25 is DNC (do not connect) per Table 7-1 and Table 7-2.; The VQFN exposed thermal pad is listed as PAD in Table 7-2 and is not a numbered pin; it is included",+ "exposed pad 41 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 48,+ "cost_usd": 0.2651,+ "at": "2026-10-07T23:09:28"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430fr2476",+ "pages": 119,+ "sha256": "c5ddbe428514a331",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430fr2475trhar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430fr2475trhar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "2104dd2e2d2db355a5afbf0a963ca9226c6f5a57427aff5754c01a50f462c9c9",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}