component
MSP430FR2110IPW16R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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page.json+8−5@@ -70,13 +70,13 @@ "number": "4", "name": "RST/NMI/SBWTDIO", "type": "bidirectional",- "description": "Reset input (active low) or configurable as NMI non-maskable interrupt input; serves as SBWTDIO Spy-Bi-Wire data bidirectional pin in debug mode; 47k\u03a9 external pullup or 10nF internal/external pulldown required per section 7.5."+ "description": "Reset input (active low) or configurable as NMI non-maskable interrupt input; serves as SBWTDIO Spy-Bi-Wire data bidirectional pin in debug mode; 47kΩ external pullup or 10nF internal/external pulldown required per section 7.5." }, { "number": "5", "name": "DVCC", "type": "power_in",- "description": "Digital power supply voltage input 1.8V to 3.6V with 4.7\u00b5F to 10\u00b5F bypass capacitor and 100nF low-ESR ceramic capacitor recommended per section 8.3."+ "description": "Digital power supply voltage input 1.8V to 3.6V with 4.7µF to 10µF bypass capacitor and 100nF low-ESR ceramic capacitor recommended per section 8.3." }, { "number": "6",@@ -112,7 +112,7 @@ "number": "11", "name": "P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+", "type": "bidirectional",- "description": "Port 1.7 general I/O; alternates to UCA0TXD UART transmit, UCA0SIMO SPI slave input/master output, TB0.2 Timer_B0 CCR2, JTAG TDO output, A7 ADC analog input, or VREF+ 1.2V reference output (1.158-1.242V, 30\u00b5V/\u00b0C typical); disabled during JTAG debug."+ "description": "Port 1.7 general I/O; alternates to UCA0TXD UART transmit, UCA0SIMO SPI slave input/master output, TB0.2 Timer_B0 CCR2, JTAG TDO output, A7 ADC analog input, or VREF+ 1.2V reference output (1.158-1.242V, 30µV/°C typical); disabled during JTAG debug." }, { "number": "12",@@ -156,7 +156,7 @@ "consensus": "agreed", "guards": "pin_guards 0.1: passed", "guard_notes": [- "extractor flagged: ADC function note: ADC module and analog functions (A0\u2013A7, Veref\u00b1, temperature sensor) are available; JTAG debug mode: Pins 11, 12, 13, 14 (P1.4\u2013P1.7) are disabled for general I/O when TEST pin is held "+ "extractor flagged: ADC function note: ADC module and analog functions (A0–A7, Veref±, temperature sensor) are available; JTAG debug mode: Pins 11, 12, 13, 14 (P1.4–P1.7) are disabled for general I/O when TEST pin is held " ], "pages_sent": 87, "cost_usd": 0.9648,@@ -222,5 +222,8 @@ "docs/msp430fr2110ipw16r-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }