component
MSP430FE4252IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# MSP430FE4252IPMR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++MSP430FE4252IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DVCC | power_in | Digital supply voltage, positive terminal. |+| 2 | I1+ | input | Current 1 positive analog input, internally connected to SD16 Channel 0 A0+; short unused analog input pairs to AVSS as recommended in Note 1. |+| 3 | I1− | input | Current 1 negative analog input, internally connected to SD16 Channel 0 A0−; short unused analog input pairs to AVSS as recommended in Note 1. |+| 4 | NC | unconnected | Not connected; connection to analog ground (AVSS) is recommended. |+| 5 | NC | unconnected | Not connected; connection to analog ground (AVSS) is recommended. |+| 6 | V1+ | input | Voltage 1 positive analog input, internally connected to SD16 Channel 1 A0+; short unused analog input pairs to AVSS as recommended in Note 1. |+| 7 | V1− | input | Voltage 1 negative analog input, internally connected to SD16 Channel 1 A0−; short unused analog input pairs to AVSS as recommended in Note 1. |+| 8 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |+| 9 | XOUT | output | Output terminal of crystal oscillator XT1. |+| 10 | VREF | power_in | Input for an external reference voltage or internal reference voltage output, which can be used as mid-voltage. |+| 11 | P2.2/STE0 | bidirectional | General-purpose digital I/O; slave transmit enable for USART0/SPI mode. |+| 12 | S0 | output | LCD segment output 0. |+| 13 | S1 | output | LCD segment output 1. |+| 14 | S2 | output | LCD segment output 2. |+| 15 | S3 | output | LCD segment output 3. |+| 16 | S4 | output | LCD segment output 4. |+| 17 | S5 | output | LCD segment output 5. |+| 18 | S6 | output | LCD segment output 6. |+| 19 | S7 | output | LCD segment output 7. |+| 20 | S8 | output | LCD segment output 8. |+| 21 | S9 | output | LCD segment output 9. |+| 22 | S10 | output | LCD segment output 10. |+| 23 | S11 | output | LCD segment output 11. |+| 24 | S12 | output | LCD segment output 12. |+| 25 | S13 | output | LCD segment output 13. |+| 26 | S14 | output | LCD segment output 14. |+| 27 | S15 | output | LCD segment output 15. |+| 28 | S16 | output | LCD segment output 16. |+| 29 | S17 | output | LCD segment output 17. |+| 30 | S18 | output | LCD segment output 18. |+| 31 | S19 | output | LCD segment output 19. |+| 32 | S20 | output | LCD segment output 20. |+| 33 | S21 | output | LCD segment output 21. |+| 34 | S22 | output | LCD segment output 22. |+| 35 | S23 | output | LCD segment output 23. |+| 36 | COM0 | output | Common output used for LCD backplane 0 (COM0−3 are the LCD backplanes). |+| 37 | COM1 | output | Common output used for LCD backplane 1 (COM0−3 are the LCD backplanes). |+| 38 | COM2 | output | Common output used for LCD backplane 2 (COM0−3 are the LCD backplanes). |+| 39 | COM3 | output | Common output used for LCD backplane 3 (COM0−3 are the LCD backplanes). |+| 40 | R03 | input | Input port of the fourth positive (lowest) analog LCD level (V5). |+| 41 | R13 | input | Input port of the third most positive analog LCD level (V4 or V3). |+| 42 | R23 | input | Input port of the second most positive analog LCD level (V2). |+| 43 | R33 | output | Output port of the most positive analog LCD level (V1). |+| 44 | P2.1/UCLK0/S24 | bidirectional | General-purpose digital I/O; external clock input for USART0/UART or SPI mode, clock output for USART0/SPI mode, and LCD segment output 24. |+| 45 | P2.0/TA2/S25 | bidirectional | General-purpose digital I/O; Timer_A capture input CCI2A, compare output Out2, and LCD segment output 25. |+| 46 | P1.7/SOMI0/S26 | bidirectional | General-purpose digital I/O; slave out/master in of USART0/SPI mode, and LCD segment output 26. |+| 47 | P1.6/SIMO0/S27 | bidirectional | General-purpose digital I/O; slave in/master out of USART0/SPI mode, and LCD segment output 27. |+| 48 | P1.5/TACLK/ACLK/S28 | bidirectional | General-purpose digital I/O; Timer_A and SD16 clock input TACLK, ACLK output divided by 1, 2, 4, or 8, and LCD segment output 28. |+| 49 | P1.4/S29 | bidirectional | General-purpose digital I/O and LCD segment output 29. |+| 50 | P1.3/SVSOUT/S30 | bidirectional | General-purpose digital I/O; SVS comparator output and LCD segment output 30. |+| 51 | P1.2/TA1/S31 | bidirectional | General-purpose digital I/O; Timer_A capture inputs CCI1A and CCI1B, compare output Out1, and LCD segment output 31. |+| 52 | P1.1/TA0/MCLK | bidirectional | General-purpose digital I/O; Timer_A capture input CCI0B, MCLK output, and BSL receive; TA0 is only an input on this pin. |+| 53 | P1.0/TA0 | bidirectional | General-purpose digital I/O; Timer_A capture input CCI0A, compare output Out0, and BSL transmit. |+| 54 | TDO/TDI | bidirectional | Test data output port; TDO/TDI is the data output or programming data input terminal. |+| 55 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to TDI. |+| 56 | TMS | input | Test mode select; used as an input port for device programming and test. |+| 57 | TCK | input | Test clock; the clock input port for device programming and test. |+| 58 | RST/NMI | input | Reset input or nonmaskable interrupt input port. |+| 59 | P2.5/URXD0 | bidirectional | General-purpose digital I/O; receive data input for USART0 in UART mode. |+| 60 | P2.4/UTXD0 | bidirectional | General-purpose digital I/O; transmit data output for USART0 in UART mode. |+| 61 | P2.3/SVSIN | bidirectional | General-purpose digital I/O; analog input to the brownout and supply voltage supervisor. |+| 62 | AVSS | power_in | Analog supply voltage, negative terminal; supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry. |+| 63 | DVSS | power_in | Digital supply voltage, negative terminal. |+| 64 | AVCC | power_in | Analog supply voltage, positive terminal; supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry and must not power up prior to DVCC. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-64(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `MSP430FE4252IPMR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `msp430fe4252ipmr-etched.step` / `msp430fe4252ipmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fe4252ipmr.step` / `msp430fe4252ipmr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fe4272) (52 pp, sha256 `7b5b56cbebee669f`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fe4252ipmr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430fe4252ipmr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430fe4252ipmr.kicad_sym",+ "msp430fe4252ipmr.kicad_mod",+ "msp430fe4252ipmr.glb",+ "msp430fe4252ipmr.step",+ "msp430fe4252ipmr.lbr",+ "docs/hero.png",+ "docs/msp430fe4252ipmr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430fe4252ipmr-hero.glb",+ "msp430fe4252ipmr-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430FE4252IPMR",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fe4272",+ "parts": {+ "symbol": "msp430fe4252ipmr.kicad_sym",+ "footprint": "msp430fe4252ipmr.kicad_mod",+ "model_3d": "msp430fe4252ipmr-hero.glb",+ "model_3d_plain": "msp430fe4252ipmr.glb",+ "model_3d_step": "msp430fe4252ipmr-etched.step",+ "model_3d_step_plain": "msp430fe4252ipmr.step",+ "lbr": "msp430fe4252ipmr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2053496",+ "digikey": "296-23732-2-ND",+ "mouser": "595-MSP430FE4252IPMR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:00:27Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-23732-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-MSP430FE4252IPMR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital supply voltage, positive terminal."+ },+ {+ "number": "2",+ "name": "I1+",+ "type": "input",+ "description": "Current 1 positive analog input, internally connected to SD16 Channel 0 A0+; short unused analog input pairs to AVSS as recommended in Note 1."+ },+ {+ "number": "3",+ "name": "I1−",+ "type": "input",+ "description": "Current 1 negative analog input, internally connected to SD16 Channel 0 A0−; short unused analog input pairs to AVSS as recommended in Note 1."+ },+ {+ "number": "4",+ "name": "NC",+ "type": "unconnected",+ "description": "Not connected; connection to analog ground (AVSS) is recommended."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "Not connected; connection to analog ground (AVSS) is recommended."+ },+ {+ "number": "6",+ "name": "V1+",+ "type": "input",+ "description": "Voltage 1 positive analog input, internally connected to SD16 Channel 1 A0+; short unused analog input pairs to AVSS as recommended in Note 1."+ },+ {+ "number": "7",+ "name": "V1−",+ "type": "input",+ "description": "Voltage 1 negative analog input, internally connected to SD16 Channel 1 A0−; short unused analog input pairs to AVSS as recommended in Note 1."+ },+ {+ "number": "8",+ "name": "XIN",+ "type": "input",+ "description": "Input port for crystal oscillator XT1; standard or watch crystals can be connected."+ },+ {+ "number": "9",+ "name": "XOUT",+ "type": "output",+ "description": "Output terminal of crystal oscillator XT1."+ },+ {+ "number": "10",+ "name": "VREF",+ "type": "power_in",+ "description": "Input for an external reference voltage or internal reference voltage output, which can be used as mid-voltage."+ },+ {+ "number": "11",+ "name": "P2.2/STE0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; slave transmit enable for USART0/SPI mode."+ },+ {+ "number": "12",+ "name": "S0",+ "type": "output",+ "description": "LCD segment output 0."+ },+ {+ "number": "13",+ "name": "S1",+ "type": "output",+ "description": "LCD segment output 1."+ },+ {+ "number": "14",+ "name": "S2",+ "type": "output",+ "description": "LCD segment output 2."+ },+ {+ "number": "15",+ "name": "S3",+ "type": "output",+ "description": "LCD segment output 3."+ },+ {+ "number": "16",+ "name": "S4",+ "type": "output",+ "description": "LCD segment output 4."+ },+ {+ "number": "17",+ "name": "S5",+ "type": "output",+ "description": "LCD segment output 5."+ },+ {+ "number": "18",+ "name": "S6",+ "type": "output",+ "description": "LCD segment output 6."+ },+ {+ "number": "19",+ "name": "S7",+ "type": "output",+ "description": "LCD segment output 7."+ },+ {+ "number": "20",+ "name": "S8",+ "type": "output",+ "description": "LCD segment output 8."+ },+ {+ "number": "21",+ "name": "S9",+ "type": "output",+ "description": "LCD segment output 9."+ },+ {+ "number": "22",+ "name": "S10",+ "type": "output",+ "description": "LCD segment output 10."+ },+ {+ "number": "23",+ "name": "S11",+ "type": "output",+ "description": "LCD segment output 11."+ },+ {+ "number": "24",+ "name": "S12",+ "type": "output",+ "description": "LCD segment output 12."+ },+ {+ "number": "25",+ "name": "S13",+ "type": "output",+ "description": "LCD segment output 13."+ },+ {+ "number": "26",+ "name": "S14",+ "type": "output",+ "description": "LCD segment output 14."+ },+ {+ "number": "27",+ "name": "S15",+ "type": "output",+ "description": "LCD segment output 15."+ },+ {+ "number": "28",+ "name": "S16",+ "type": "output",+ "description": "LCD segment output 16."+ },+ {+ "number": "29",+ "name": "S17",+ "type": "output",+ "description": "LCD segment output 17."+ },+ {+ "number": "30",+ "name": "S18",+ "type": "output",+ "description": "LCD segment output 18."+ },+ {+ "number": "31",+ "name": "S19",+ "type": "output",+ "description": "LCD segment output 19."+ },+ {+ "number": "32",+ "name": "S20",+ "type": "output",+ "description": "LCD segment output 20."+ },+ {+ "number": "33",+ "name": "S21",+ "type": "output",+ "description": "LCD segment output 21."+ },+ {+ "number": "34",+ "name": "S22",+ "type": "output",+ "description": "LCD segment output 22."+ },+ {+ "number": "35",+ "name": "S23",+ "type": "output",+ "description": "LCD segment output 23."+ },+ {+ "number": "36",+ "name": "COM0",+ "type": "output",+ "description": "Common output used for LCD backplane 0 (COM0−3 are the LCD backplanes)."+ },+ {+ "number": "37",+ "name": "COM1",+ "type": "output",+ "description": "Common output used for LCD backplane 1 (COM0−3 are the LCD backplanes)."+ },+ {+ "number": "38",+ "name": "COM2",+ "type": "output",+ "description": "Common output used for LCD backplane 2 (COM0−3 are the LCD backplanes)."+ },+ {+ "number": "39",+ "name": "COM3",+ "type": "output",+ "description": "Common output used for LCD backplane 3 (COM0−3 are the LCD backplanes)."+ },+ {+ "number": "40",+ "name": "R03",+ "type": "input",+ "description": "Input port of the fourth positive (lowest) analog LCD level (V5)."+ },+ {+ "number": "41",+ "name": "R13",+ "type": "input",+ "description": "Input port of the third most positive analog LCD level (V4 or V3)."+ },+ {+ "number": "42",+ "name": "R23",+ "type": "input",+ "description": "Input port of the second most positive analog LCD level (V2)."+ },+ {+ "number": "43",+ "name": "R33",+ "type": "output",+ "description": "Output port of the most positive analog LCD level (V1)."+ },+ {+ "number": "44",+ "name": "P2.1/UCLK0/S24",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; external clock input for USART0/UART or SPI mode, clock output for USART0/SPI mode, and LCD segment output 24."+ },+ {+ "number": "45",+ "name": "P2.0/TA2/S25",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; Timer_A capture input CCI2A, compare output Out2, and LCD segment output 25."+ },+ {+ "number": "46",+ "name": "P1.7/SOMI0/S26",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; slave out/master in of USART0/SPI mode, and LCD segment output 26."+ },+ {+ "number": "47",+ "name": "P1.6/SIMO0/S27",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; slave in/master out of USART0/SPI mode, and LCD segment output 27."+ },+ {+ "number": "48",+ "name": "P1.5/TACLK/ACLK/S28",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; Timer_A and SD16 clock input TACLK, ACLK output divided by 1, 2, 4, or 8, and LCD segment output 28."+ },+ {+ "number": "49",+ "name": "P1.4/S29",+ "type": "bidirectional",+ "description": "General-purpose digital I/O and LCD segment output 29."+ },+ {+ "number": "50",+ "name": "P1.3/SVSOUT/S30",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; SVS comparator output and LCD segment output 30."+ },+ {+ "number": "51",+ "name": "P1.2/TA1/S31",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; Timer_A capture inputs CCI1A and CCI1B, compare output Out1, and LCD segment output 31."+ },+ {+ "number": "52",+ "name": "P1.1/TA0/MCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; Timer_A capture input CCI0B, MCLK output, and BSL receive; TA0 is only an input on this pin."+ },+ {+ "number": "53",+ "name": "P1.0/TA0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; Timer_A capture input CCI0A, compare output Out0, and BSL transmit."+ },+ {+ "number": "54",+ "name": "TDO/TDI",+ "type": "bidirectional",+ "description": "Test data output port; TDO/TDI is the data output or programming data input terminal."+ },+ {+ "number": "55",+ "name": "TDI/TCLK",+ "type": "input",+ "description": "Test data input or test clock input; the device protection fuse is connected to TDI."+ },+ {+ "number": "56",+ "name": "TMS",+ "type": "input",+ "description": "Test mode select; used as an input port for device programming and test."+ },+ {+ "number": "57",+ "name": "TCK",+ "type": "input",+ "description": "Test clock; the clock input port for device programming and test."+ },+ {+ "number": "58",+ "name": "RST/NMI",+ "type": "input",+ "description": "Reset input or nonmaskable interrupt input port."+ },+ {+ "number": "59",+ "name": "P2.5/URXD0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; receive data input for USART0 in UART mode."+ },+ {+ "number": "60",+ "name": "P2.4/UTXD0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; transmit data output for USART0 in UART mode."+ },+ {+ "number": "61",+ "name": "P2.3/SVSIN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; analog input to the brownout and supply voltage supervisor."+ },+ {+ "number": "62",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog supply voltage, negative terminal; supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry."+ },+ {+ "number": "63",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital supply voltage, negative terminal."+ },+ {+ "number": "64",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog supply voltage, positive terminal; supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry and must not power up prior to DVCC."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package is taken from the ordering addendum (LQFP (PM), 64 pins, MSP430FE4252IPMR). The 10x10 mm bod; The datasheet is the MSP430FE42x2 family document; the terminal table covers all family members. Pin; Pins 4 and 5 are NC. The terminal table lists their type as I, but they are typed here as unconnecte"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0951,+ "at": "2026-10-08T14:59:55"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430fe4272",+ "pages": 52,+ "sha256": "7b5b56cbebee669f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430fe4252ipmr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430fe4252ipmr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "532b2201583e6ffc166bf18e6ef557e0a08afa033f02800cfd0820175511d84e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}