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MSP430F6723AIPZR
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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+137@@ -0,0 +1,137 @@+# MSP430F6723AIPZR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)++MSP430F6723AIPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SD0P0 | input | SD24_B positive analog input for converter 0; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA. |+| 2 | SD0N0 | input | SD24_B negative analog input for converter 0; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA. |+| 3 | SD1P0 | input | SD24_B positive analog input for converter 1; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA. |+| 4 | SD1N0 | input | SD24_B negative analog input for converter 1; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA. |+| 5 | NC | unconnected | No connection on MSP430F672xA devices; this pin is SD2P0 (SD24_B positive input for converter 2) only on MSP430F673xA devices. |+| 6 | NC | unconnected | No connection on MSP430F672xA devices; this pin is SD2N0 (SD24_B negative input for converter 2) only on MSP430F673xA devices. |+| 7 | VREF | power_in | SD24_B external reference voltage pin. |+| 8 | AVSS | power_in | Analog ground supply; AVSS must be at the same potential as DVSS (0 V). |+| 9 | AVCC | power_in | Analog power supply; TI recommends powering AVCC and DVCC from the same source, with at most 0.3 V difference during power-up and operation. |+| 10 | VASYS | power_in | Analog power supply selected among AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor CVSYS (Table 5-18). |+| 11 | P9.1/A5 | bidirectional | Digital I/O P9.1 powered from DVCC (OFF after BOR) that also serves as ADC10_A analog input A5; set P9SEL to disable the output driver and Schmitt trigger for analog use. |+| 12 | P9.2/A4 | bidirectional | Digital I/O P9.2 powered from DVCC (OFF after BOR) that also serves as ADC10_A analog input A4; set P9SEL to disable the output driver and Schmitt trigger for analog use. |+| 13 | P9.3/A3 | bidirectional | Digital I/O P9.3 powered from DVCC (OFF after BOR) that also serves as ADC10_A analog input A3; set P9SEL to disable the output driver and Schmitt trigger for analog use. |+| 14 | P1.0/PM_TA0.0/VeREF-/A2 | bidirectional | Port P1.0 I/O with port interrupt; alternates are mappable Timer_A TA0 CCR0 capture/compare, VeREF- (negative ADC reference terminal for an external reference) and ADC10_A input A2. |+| 15 | P1.1/PM_TA0.1/VeREF+/A1 | bidirectional | Port P1.1 I/O with port interrupt; alternates are mappable Timer_A TA0 CCR1 capture/compare, VeREF+ (positive ADC reference terminal for an external reference) and ADC10_A input A1. |+| 16 | P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 | bidirectional | Port P1.2 I/O with port interrupt; alternates are mappable eUSCI_A0 UART RXD / SPI SOMI and ADC10_A input A0. |+| 17 | P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 | bidirectional | Port P1.3 I/O with port interrupt; alternates are mappable eUSCI_A0 UART TXD / SPI SIMO and R03, the input/output port of the lowest analog LCD voltage (V5). |+| 18 | AUXVCC2 | power_in | Auxiliary power supply AUXVCC2; maximum load current is 20 mA for core and I/O and 5 mA for analog modules. |+| 19 | AUXVCC1 | power_in | Auxiliary power supply AUXVCC1; maximum load current is 20 mA for core and I/O and 5 mA for analog modules. |+| 20 | VDSYS | power_in | Digital power supply selected between DVCC, AUXVCC1 and AUXVCC2; must be connected externally on board and to the recommended capacitor CVSYS. |+| 21 | DVCC | power_in | Digital power supply; supply voltage is 1.8 V to 3.6 V depending on the PMMCOREVx setting, with a maximum load of 20 mA for core and I/O. |+| 22 | DVSS | power_in | Digital ground supply, the 0 V reference for the device supplies. |+| 23 | VCORE | power_out | Regulated core power supply for internal use only; no external DC loading or voltage may be applied and only the recommended capacitor CVCORE (470 nF) should be connected. |+| 24 | XIN | input | Input terminal for the 32 kHz crystal oscillator; connect to DVSS if unused. |+| 25 | XOUT | output | Output terminal for the crystal oscillator; leave open if unused. |+| 26 | AUXVCC3 | power_in | Auxiliary power supply AUXVCC3 dedicated to the backup subsystem (XT1, RTC_C and backup RAM). |+| 27 | P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 | bidirectional | Port P1.4 I/O with port interrupt; alternates are mappable eUSCI_A1 UART RXD / SPI SOMI, LCDREF (external LCD reference voltage input) and R13 (third most positive LCD voltage V3 or V4). |+| 28 | P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 | bidirectional | Port P1.5 I/O with port interrupt; alternates are mappable eUSCI_A1 UART TXD / SPI SIMO and R23 (second most positive LCD voltage V2). |+| 29 | LCDCAP/R33 | bidirectional | LCD capacitor connection that must be connected to DVSS if not used; R33 is the input/output port of the most positive analog LCD voltage (V1). |+| 30 | P8.4/TA1.0 | bidirectional | Digital I/O P8.4 powered from DVCC with Timer_A TA1 CCR0 capture input / compare output alternate function. |+| 31 | P8.5/TA1.1 | bidirectional | Digital I/O P8.5 powered from DVCC with Timer_A TA1 CCR1 capture input / compare output alternate function. |+| 32 | COM0 | output | LCD common output COM0 for the LCD backplane, powered from DVCC. |+| 33 | COM1 | output | LCD common output COM1 for the LCD backplane, powered from DVCC. |+| 34 | COM2 | output | LCD common output COM2 for the LCD backplane, powered from DVCC. |+| 35 | COM3 | output | LCD common output COM3 for the LCD backplane, powered from DVCC. |+| 36 | P1.6/PM_UCA0CLK/COM4 | bidirectional | Port P1.6 I/O; alternates are mappable eUSCI_A0 clock input/output and LCD common output COM4. |+| 37 | P1.7/PM_UCB0CLK/COM5 | bidirectional | Port P1.7 I/O; alternates are mappable eUSCI_B0 clock input/output and LCD common output COM5. |+| 38 | P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6 | bidirectional | Port P2.0 I/O with port interrupt; alternates are mappable eUSCI_B0 SPI SOMI / I2C clock (open drain) and LCD common output COM6. |+| 39 | P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7 | bidirectional | Port P2.1 I/O with port interrupt; alternates are mappable eUSCI_B0 SPI SIMO / I2C data (open drain) and LCD common output COM7. |+| 40 | P8.6/TA2.0 | bidirectional | Digital I/O P8.6 powered from DVCC with Timer_A TA2 CCR0 capture input / compare output alternate function. |+| 41 | P8.7/TA2.1 | bidirectional | Digital I/O P8.7 powered from DVCC with Timer_A TA2 CCR1 capture input / compare output alternate function. |+| 42 | P9.0/TACLK/RTCCLK | bidirectional | Digital I/O P9.0 powered from DVCC with Timer_A clock input TACLK and RTC_C clock output RTCCLK as alternate functions. |+| 43 | P2.2/PM_UCA2RXD/PM_UCA2SOMI | bidirectional | Port P2.2 I/O with port interrupt; alternates are mappable eUSCI_A2 UART RXD / SPI SOMI. |+| 44 | P2.3/PM_UCA2TXD/PM_UCA2SIMO | bidirectional | Port P2.3 I/O with port interrupt; alternates are mappable eUSCI_A2 UART TXD / SPI SIMO. |+| 45 | P2.4/PM_UCA1CLK | bidirectional | Port P2.4 I/O with port interrupt; alternate is mappable eUSCI_A1 clock input/output. |+| 46 | P2.5/PM_UCA2CLK | bidirectional | Port P2.5 I/O with port interrupt; alternate is mappable eUSCI_A2 clock input/output. |+| 47 | P2.6/PM_TA1.0 | bidirectional | Port P2.6 I/O with port interrupt; alternate is mappable Timer_A TA1 CCR0 capture/compare. |+| 48 | P2.7/PM_TA1.1 | bidirectional | Port P2.7 I/O with port interrupt; alternate is mappable Timer_A TA1 CCR1 capture/compare. |+| 49 | P3.0/PM_TA2.0/BSL_TX | bidirectional | Port P3.0 I/O with mappable functions; alternates are Timer_A TA2 CCR0 capture/compare and bootloader data transmit BSL_TX. |+| 50 | P3.1/PM_TA2.1/BSL_RX | bidirectional | Port P3.1 I/O with mappable functions; alternates are Timer_A TA2 CCR1 capture/compare and bootloader data receive BSL_RX. |+| 51 | P3.2/PM_TACLK/PM_RTCCLK | bidirectional | Port P3.2 I/O with mappable functions; alternates are Timer_A clock input TACLK and RTC_C clock output RTCCLK. |+| 52 | P3.3/PM_TA0.2 | bidirectional | Port P3.3 I/O with mappable function; alternate is Timer_A TA0 CCR2 capture/compare. |+| 53 | P3.4/PM_SDCLK/S39 | bidirectional | Port P3.4 I/O with mappable function; alternates are SD24_B bit stream clock I/O and LCD segment output S39. |+| 54 | P3.5/PM_SD0DIO/S38 | bidirectional | Port P3.5 I/O with mappable function; alternates are SD24_B converter 0 bit stream data I/O and LCD segment output S38. |+| 55 | P3.6/PM_SD1DIO/S37 | bidirectional | Port P3.6 I/O with mappable function; alternates are SD24_B converter 1 bit stream data I/O and LCD segment output S37. |+| 56 | P3.7/PM_NONE/S36 | bidirectional | On MSP430F672xA devices the SD2DIO mapping is not available (PM_NONE), so P3.7 is digital I/O with LCD segment output S36. |+| 57 | P4.0/S35 | bidirectional | Digital I/O P4.0 powered from DVCC (OFF after BOR) with LCD segment output S35. |+| 58 | P4.1/S34 | bidirectional | Digital I/O P4.1 powered from DVCC (OFF after BOR) with LCD segment output S34. |+| 59 | P4.2/S33 | bidirectional | Digital I/O P4.2 powered from DVCC (OFF after BOR) with LCD segment output S33. |+| 60 | P4.3/S32 | bidirectional | Digital I/O P4.3 powered from DVCC (OFF after BOR) with LCD segment output S32. |+| 61 | P4.4/S31 | bidirectional | Digital I/O P4.4 powered from DVCC (OFF after BOR) with LCD segment output S31. |+| 62 | P4.5/S30 | bidirectional | Digital I/O P4.5 powered from DVCC (OFF after BOR) with LCD segment output S30. |+| 63 | P4.6/S29 | bidirectional | Digital I/O P4.6 powered from DVCC (OFF after BOR) with LCD segment output S29. |+| 64 | P4.7/S28 | bidirectional | Digital I/O P4.7 powered from DVCC (OFF after BOR) with LCD segment output S28. |+| 65 | P5.0/S27 | bidirectional | Digital I/O P5.0 powered from DVCC (OFF after BOR) with LCD segment output S27. |+| 66 | P5.1/S26 | bidirectional | Digital I/O P5.1 powered from DVCC (OFF after BOR) with LCD segment output S26. |+| 67 | P5.2/S25 | bidirectional | Digital I/O P5.2 powered from DVCC (OFF after BOR) with LCD segment output S25. |+| 68 | P5.3/S24 | bidirectional | Digital I/O P5.3 powered from DVCC (OFF after BOR) with LCD segment output S24. |+| 69 | P5.4/S23 | bidirectional | Digital I/O P5.4 powered from DVCC (OFF after BOR) with LCD segment output S23. |+| 70 | P5.5/S22 | bidirectional | Digital I/O P5.5 powered from DVCC (OFF after BOR) with LCD segment output S22. |+| 71 | P5.6/S21 | bidirectional | Digital I/O P5.6 powered from DVCC (OFF after BOR) with LCD segment output S21. |+| 72 | P5.7/S20 | bidirectional | Digital I/O P5.7 powered from DVCC (OFF after BOR) with LCD segment output S20. |+| 73 | P6.0/S19 | bidirectional | Digital I/O P6.0 powered from DVCC (OFF after BOR) with LCD segment output S19. |+| 74 | DVSYS | power_in | Digital power supply for I/Os; must be connected externally on board for proper device operation. |+| 75 | DVSS | power_in | Digital ground supply. |+| 76 | P6.1/S18 | bidirectional | Digital I/O P6.1 powered from DVCC (OFF after BOR) with LCD segment output S18. |+| 77 | P6.2/S17 | bidirectional | Digital I/O P6.2 powered from DVCC (OFF after BOR) with LCD segment output S17. |+| 78 | P6.3/S16 | bidirectional | Digital I/O P6.3 powered from DVCC (OFF after BOR) with LCD segment output S16. |+| 79 | P6.4/S15 | bidirectional | Digital I/O P6.4 powered from DVCC (OFF after BOR) with LCD segment output S15. |+| 80 | P6.5/S14 | bidirectional | Digital I/O P6.5 powered from DVCC (OFF after BOR) with LCD segment output S14. |+| 81 | P6.6/S13 | bidirectional | Digital I/O P6.6 powered from DVCC (OFF after BOR) with LCD segment output S13. |+| 82 | P6.7/S12 | bidirectional | Digital I/O P6.7 powered from DVCC (OFF after BOR) with LCD segment output S12. |+| 83 | P7.0/S11 | bidirectional | Digital I/O P7.0 powered from DVCC (OFF after BOR) with LCD segment output S11. |+| 84 | P7.1/S10 | bidirectional | Digital I/O P7.1 powered from DVCC (OFF after BOR) with LCD segment output S10. |+| 85 | P7.2/S9 | bidirectional | Digital I/O P7.2 powered from DVCC (OFF after BOR) with LCD segment output S9. |+| 86 | P7.3/S8 | bidirectional | Digital I/O P7.3 powered from DVCC (OFF after BOR) with LCD segment output S8. |+| 87 | P7.4/S7 | bidirectional | Digital I/O P7.4 powered from DVCC (OFF after BOR) with LCD segment output S7. |+| 88 | P7.5/S6 | bidirectional | Digital I/O P7.5 powered from DVCC (OFF after BOR) with LCD segment output S6. |+| 89 | P7.6/S5 | bidirectional | Digital I/O P7.6 powered from DVCC (OFF after BOR) with LCD segment output S5. |+| 90 | P7.7/S4 | bidirectional | Digital I/O P7.7 powered from DVCC (OFF after BOR) with LCD segment output S4. |+| 91 | P8.0/S3 | bidirectional | Digital I/O P8.0 powered from DVCC (OFF after BOR) with LCD segment output S3. |+| 92 | P8.1/S2 | bidirectional | Digital I/O P8.1 powered from DVCC (OFF after BOR) with LCD segment output S2. |+| 93 | P8.2/S1 | bidirectional | Digital I/O P8.2 powered from DVCC (OFF after BOR) with LCD segment output S1. |+| 94 | P8.3/S0 | bidirectional | Digital I/O P8.3 powered from DVCC (OFF after BOR) with LCD segment output S0. |+| 95 | TEST/SBWTCK | input | Test mode pin that selects digital I/O on the JTAG pins; it always has an internal pulldown enabled and doubles as Spy-Bi-Wire input clock SBWTCK. |+| 96 | PJ.0/SMCLK/TDO | bidirectional | Port PJ.0 I/O (OFF after BOR); alternates are SMCLK clock output and JTAG test data output TDO. |+| 97 | PJ.1/MCLK/TDI/TCLK | bidirectional | Port PJ.1 I/O (OFF after BOR); alternates are MCLK clock output and JTAG test data input TDI / test clock input TCLK. |+| 98 | PJ.2/ADC10CLK/TMS | bidirectional | Port PJ.2 I/O (OFF after BOR); alternates are ADC10_A clock output and JTAG test mode select input TMS. |+| 99 | PJ.3/ACLK/TCK | bidirectional | Port PJ.3 I/O (OFF after BOR); alternates are ACLK clock output and JTAG test clock input TCK. |+| 100 | RST/NMI/SBWTDIO | input | Reset input active low with internal pullup enabled by default; alternates are nonmaskable interrupt input NMI and Spy-Bi-Wire data I/O SBWTDIO. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-100(14x14) |+| Category | Embedded Processors & Controllers |+| Pins | 100 |++## CAD (KiCad official)++- Symbol: `MSP430F6723AIPZR`+- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`+- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)+- 3D model files: `msp430f6723aipzr-etched.step` / `msp430f6723aipzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f6723aipzr.step` / `msp430f6723aipzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f6720a) (168 pp, sha256 `9f50329e4202500f`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430f6723aipzr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430f6723aipzr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430f6723aipzr.kicad_sym",+ "msp430f6723aipzr.kicad_mod",+ "msp430f6723aipzr.glb",+ "msp430f6723aipzr.step",+ "msp430f6723aipzr.lbr",+ "docs/hero.png",+ "docs/msp430f6723aipzr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430f6723aipzr-hero.glb",+ "msp430f6723aipzr-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430F6723AIPZR",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-100(14x14)",+ "pin_count": 100,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430f6720a",+ "parts": {+ "symbol": "msp430f6723aipzr.kicad_sym",+ "footprint": "msp430f6723aipzr.kicad_mod",+ "model_3d": "msp430f6723aipzr-hero.glb",+ "model_3d_plain": "msp430f6723aipzr.glb",+ "model_3d_step": "msp430f6723aipzr-etched.step",+ "model_3d_step_plain": "msp430f6723aipzr.step",+ "lbr": "msp430f6723aipzr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2056282",+ "digikey": "MSP430F6723AIPZR-ND",+ "mouser": "595-MSP430F6723AIPZR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:03:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "MSP430F6723AIPZR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-MSP430F6723AIPZR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SD0P0",+ "type": "input",+ "description": "SD24_B positive analog input for converter 0; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA."+ },+ {+ "number": "2",+ "name": "SD0N0",+ "type": "input",+ "description": "SD24_B negative analog input for converter 0; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA."+ },+ {+ "number": "3",+ "name": "SD1P0",+ "type": "input",+ "description": "SD24_B positive analog input for converter 1; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA."+ },+ {+ "number": "4",+ "name": "SD1N0",+ "type": "input",+ "description": "SD24_B negative analog input for converter 1; a protection diode connects to VCC only (not VSS) and diode current at this pin is limited to 2 mA."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection on MSP430F672xA devices; this pin is SD2P0 (SD24_B positive input for converter 2) only on MSP430F673xA devices."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection on MSP430F672xA devices; this pin is SD2N0 (SD24_B negative input for converter 2) only on MSP430F673xA devices."+ },+ {+ "number": "7",+ "name": "VREF",+ "type": "power_in",+ "description": "SD24_B external reference voltage pin."+ },+ {+ "number": "8",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground supply; AVSS must be at the same potential as DVSS (0 V)."+ },+ {+ "number": "9",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog power supply; TI recommends powering AVCC and DVCC from the same source, with at most 0.3 V difference during power-up and operation."+ },+ {+ "number": "10",+ "name": "VASYS",+ "type": "power_in",+ "description": "Analog power supply selected among AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor CVSYS (Table 5-18)."+ },+ {+ "number": "11",+ "name": "P9.1/A5",+ "type": "bidirectional",+ "description": "Digital I/O P9.1 powered from DVCC (OFF after BOR) that also serves as ADC10_A analog input A5; set P9SEL to disable the output driver and Schmitt trigger for analog use."+ },+ {+ "number": "12",+ "name": "P9.2/A4",+ "type": "bidirectional",+ "description": "Digital I/O P9.2 powered from DVCC (OFF after BOR) that also serves as ADC10_A analog input A4; set P9SEL to disable the output driver and Schmitt trigger for analog use."+ },+ {+ "number": "13",+ "name": "P9.3/A3",+ "type": "bidirectional",+ "description": "Digital I/O P9.3 powered from DVCC (OFF after BOR) that also serves as ADC10_A analog input A3; set P9SEL to disable the output driver and Schmitt trigger for analog use."+ },+ {+ "number": "14",+ "name": "P1.0/PM_TA0.0/VeREF-/A2",+ "type": "bidirectional",+ "description": "Port P1.0 I/O with port interrupt; alternates are mappable Timer_A TA0 CCR0 capture/compare, VeREF- (negative ADC reference terminal for an external reference) and ADC10_A input A2."+ },+ {+ "number": "15",+ "name": "P1.1/PM_TA0.1/VeREF+/A1",+ "type": "bidirectional",+ "description": "Port P1.1 I/O with port interrupt; alternates are mappable Timer_A TA0 CCR1 capture/compare, VeREF+ (positive ADC reference terminal for an external reference) and ADC10_A input A1."+ },+ {+ "number": "16",+ "name": "P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0",+ "type": "bidirectional",+ "description": "Port P1.2 I/O with port interrupt; alternates are mappable eUSCI_A0 UART RXD / SPI SOMI and ADC10_A input A0."+ },+ {+ "number": "17",+ "name": "P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03",+ "type": "bidirectional",+ "description": "Port P1.3 I/O with port interrupt; alternates are mappable eUSCI_A0 UART TXD / SPI SIMO and R03, the input/output port of the lowest analog LCD voltage (V5)."+ },+ {+ "number": "18",+ "name": "AUXVCC2",+ "type": "power_in",+ "description": "Auxiliary power supply AUXVCC2; maximum load current is 20 mA for core and I/O and 5 mA for analog modules."+ },+ {+ "number": "19",+ "name": "AUXVCC1",+ "type": "power_in",+ "description": "Auxiliary power supply AUXVCC1; maximum load current is 20 mA for core and I/O and 5 mA for analog modules."+ },+ {+ "number": "20",+ "name": "VDSYS",+ "type": "power_in",+ "description": "Digital power supply selected between DVCC, AUXVCC1 and AUXVCC2; must be connected externally on board and to the recommended capacitor CVSYS."+ },+ {+ "number": "21",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital power supply; supply voltage is 1.8 V to 3.6 V depending on the PMMCOREVx setting, with a maximum load of 20 mA for core and I/O."+ },+ {+ "number": "22",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground supply, the 0 V reference for the device supplies."+ },+ {+ "number": "23",+ "name": "VCORE",+ "type": "power_out",+ "description": "Regulated core power supply for internal use only; no external DC loading or voltage may be applied and only the recommended capacitor CVCORE (470 nF) should be connected."+ },+ {+ "number": "24",+ "name": "XIN",+ "type": "input",+ "description": "Input terminal for the 32 kHz crystal oscillator; connect to DVSS if unused."+ },+ {+ "number": "25",+ "name": "XOUT",+ "type": "output",+ "description": "Output terminal for the crystal oscillator; leave open if unused."+ },+ {+ "number": "26",+ "name": "AUXVCC3",+ "type": "power_in",+ "description": "Auxiliary power supply AUXVCC3 dedicated to the backup subsystem (XT1, RTC_C and backup RAM)."+ },+ {+ "number": "27",+ "name": "P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13",+ "type": "bidirectional",+ "description": "Port P1.4 I/O with port interrupt; alternates are mappable eUSCI_A1 UART RXD / SPI SOMI, LCDREF (external LCD reference voltage input) and R13 (third most positive LCD voltage V3 or V4)."+ },+ {+ "number": "28",+ "name": "P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23",+ "type": "bidirectional",+ "description": "Port P1.5 I/O with port interrupt; alternates are mappable eUSCI_A1 UART TXD / SPI SIMO and R23 (second most positive LCD voltage V2)."+ },+ {+ "number": "29",+ "name": "LCDCAP/R33",+ "type": "bidirectional",+ "description": "LCD capacitor connection that must be connected to DVSS if not used; R33 is the input/output port of the most positive analog LCD voltage (V1)."+ },+ {+ "number": "30",+ "name": "P8.4/TA1.0",+ "type": "bidirectional",+ "description": "Digital I/O P8.4 powered from DVCC with Timer_A TA1 CCR0 capture input / compare output alternate function."+ },+ {+ "number": "31",+ "name": "P8.5/TA1.1",+ "type": "bidirectional",+ "description": "Digital I/O P8.5 powered from DVCC with Timer_A TA1 CCR1 capture input / compare output alternate function."+ },+ {+ "number": "32",+ "name": "COM0",+ "type": "output",+ "description": "LCD common output COM0 for the LCD backplane, powered from DVCC."+ },+ {+ "number": "33",+ "name": "COM1",+ "type": "output",+ "description": "LCD common output COM1 for the LCD backplane, powered from DVCC."+ },+ {+ "number": "34",+ "name": "COM2",+ "type": "output",+ "description": "LCD common output COM2 for the LCD backplane, powered from DVCC."+ },+ {+ "number": "35",+ "name": "COM3",+ "type": "output",+ "description": "LCD common output COM3 for the LCD backplane, powered from DVCC."+ },+ {+ "number": "36",+ "name": "P1.6/PM_UCA0CLK/COM4",+ "type": "bidirectional",+ "description": "Port P1.6 I/O; alternates are mappable eUSCI_A0 clock input/output and LCD common output COM4."+ },+ {+ "number": "37",+ "name": "P1.7/PM_UCB0CLK/COM5",+ "type": "bidirectional",+ "description": "Port P1.7 I/O; alternates are mappable eUSCI_B0 clock input/output and LCD common output COM5."+ },+ {+ "number": "38",+ "name": "P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6",+ "type": "bidirectional",+ "description": "Port P2.0 I/O with port interrupt; alternates are mappable eUSCI_B0 SPI SOMI / I2C clock (open drain) and LCD common output COM6."+ },+ {+ "number": "39",+ "name": "P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7",+ "type": "bidirectional",+ "description": "Port P2.1 I/O with port interrupt; alternates are mappable eUSCI_B0 SPI SIMO / I2C data (open drain) and LCD common output COM7."+ },+ {+ "number": "40",+ "name": "P8.6/TA2.0",+ "type": "bidirectional",+ "description": "Digital I/O P8.6 powered from DVCC with Timer_A TA2 CCR0 capture input / compare output alternate function."+ },+ {+ "number": "41",+ "name": "P8.7/TA2.1",+ "type": "bidirectional",+ "description": "Digital I/O P8.7 powered from DVCC with Timer_A TA2 CCR1 capture input / compare output alternate function."+ },+ {+ "number": "42",+ "name": "P9.0/TACLK/RTCCLK",+ "type": "bidirectional",+ "description": "Digital I/O P9.0 powered from DVCC with Timer_A clock input TACLK and RTC_C clock output RTCCLK as alternate functions."+ },+ {+ "number": "43",+ "name": "P2.2/PM_UCA2RXD/PM_UCA2SOMI",+ "type": "bidirectional",+ "description": "Port P2.2 I/O with port interrupt; alternates are mappable eUSCI_A2 UART RXD / SPI SOMI."+ },+ {+ "number": "44",+ "name": "P2.3/PM_UCA2TXD/PM_UCA2SIMO",+ "type": "bidirectional",+ "description": "Port P2.3 I/O with port interrupt; alternates are mappable eUSCI_A2 UART TXD / SPI SIMO."+ },+ {+ "number": "45",+ "name": "P2.4/PM_UCA1CLK",+ "type": "bidirectional",+ "description": "Port P2.4 I/O with port interrupt; alternate is mappable eUSCI_A1 clock input/output."+ },+ {+ "number": "46",+ "name": "P2.5/PM_UCA2CLK",+ "type": "bidirectional",+ "description": "Port P2.5 I/O with port interrupt; alternate is mappable eUSCI_A2 clock input/output."+ },+ {+ "number": "47",+ "name": "P2.6/PM_TA1.0",+ "type": "bidirectional",+ "description": "Port P2.6 I/O with port interrupt; alternate is mappable Timer_A TA1 CCR0 capture/compare."+ },+ {+ "number": "48",+ "name": "P2.7/PM_TA1.1",+ "type": "bidirectional",+ "description": "Port P2.7 I/O with port interrupt; alternate is mappable Timer_A TA1 CCR1 capture/compare."+ },+ {+ "number": "49",+ "name": "P3.0/PM_TA2.0/BSL_TX",+ "type": "bidirectional",+ "description": "Port P3.0 I/O with mappable functions; alternates are Timer_A TA2 CCR0 capture/compare and bootloader data transmit BSL_TX."+ },+ {+ "number": "50",+ "name": "P3.1/PM_TA2.1/BSL_RX",+ "type": "bidirectional",+ "description": "Port P3.1 I/O with mappable functions; alternates are Timer_A TA2 CCR1 capture/compare and bootloader data receive BSL_RX."+ },+ {+ "number": "51",+ "name": "P3.2/PM_TACLK/PM_RTCCLK",+ "type": "bidirectional",+ "description": "Port P3.2 I/O with mappable functions; alternates are Timer_A clock input TACLK and RTC_C clock output RTCCLK."+ },+ {+ "number": "52",+ "name": "P3.3/PM_TA0.2",+ "type": "bidirectional",+ "description": "Port P3.3 I/O with mappable function; alternate is Timer_A TA0 CCR2 capture/compare."+ },+ {+ "number": "53",+ "name": "P3.4/PM_SDCLK/S39",+ "type": "bidirectional",+ "description": "Port P3.4 I/O with mappable function; alternates are SD24_B bit stream clock I/O and LCD segment output S39."+ },+ {+ "number": "54",+ "name": "P3.5/PM_SD0DIO/S38",+ "type": "bidirectional",+ "description": "Port P3.5 I/O with mappable function; alternates are SD24_B converter 0 bit stream data I/O and LCD segment output S38."+ },+ {+ "number": "55",+ "name": "P3.6/PM_SD1DIO/S37",+ "type": "bidirectional",+ "description": "Port P3.6 I/O with mappable function; alternates are SD24_B converter 1 bit stream data I/O and LCD segment output S37."+ },+ {+ "number": "56",+ "name": "P3.7/PM_NONE/S36",+ "type": "bidirectional",+ "description": "On MSP430F672xA devices the SD2DIO mapping is not available (PM_NONE), so P3.7 is digital I/O with LCD segment output S36."+ },+ {+ "number": "57",+ "name": "P4.0/S35",+ "type": "bidirectional",+ "description": "Digital I/O P4.0 powered from DVCC (OFF after BOR) with LCD segment output S35."+ },+ {+ "number": "58",+ "name": "P4.1/S34",+ "type": "bidirectional",+ "description": "Digital I/O P4.1 powered from DVCC (OFF after BOR) with LCD segment output S34."+ },+ {+ "number": "59",+ "name": "P4.2/S33",+ "type": "bidirectional",+ "description": "Digital I/O P4.2 powered from DVCC (OFF after BOR) with LCD segment output S33."+ },+ {+ "number": "60",+ "name": "P4.3/S32",+ "type": "bidirectional",+ "description": "Digital I/O P4.3 powered from DVCC (OFF after BOR) with LCD segment output S32."+ },+ {+ "number": "61",+ "name": "P4.4/S31",+ "type": "bidirectional",+ "description": "Digital I/O P4.4 powered from DVCC (OFF after BOR) with LCD segment output S31."+ },+ {+ "number": "62",+ "name": "P4.5/S30",+ "type": "bidirectional",+ "description": "Digital I/O P4.5 powered from DVCC (OFF after BOR) with LCD segment output S30."+ },+ {+ "number": "63",+ "name": "P4.6/S29",+ "type": "bidirectional",+ "description": "Digital I/O P4.6 powered from DVCC (OFF after BOR) with LCD segment output S29."+ },+ {+ "number": "64",+ "name": "P4.7/S28",+ "type": "bidirectional",+ "description": "Digital I/O P4.7 powered from DVCC (OFF after BOR) with LCD segment output S28."+ },+ {+ "number": "65",+ "name": "P5.0/S27",+ "type": "bidirectional",+ "description": "Digital I/O P5.0 powered from DVCC (OFF after BOR) with LCD segment output S27."+ },+ {+ "number": "66",+ "name": "P5.1/S26",+ "type": "bidirectional",+ "description": "Digital I/O P5.1 powered from DVCC (OFF after BOR) with LCD segment output S26."+ },+ {+ "number": "67",+ "name": "P5.2/S25",+ "type": "bidirectional",+ "description": "Digital I/O P5.2 powered from DVCC (OFF after BOR) with LCD segment output S25."+ },+ {+ "number": "68",+ "name": "P5.3/S24",+ "type": "bidirectional",+ "description": "Digital I/O P5.3 powered from DVCC (OFF after BOR) with LCD segment output S24."+ },+ {+ "number": "69",+ "name": "P5.4/S23",+ "type": "bidirectional",+ "description": "Digital I/O P5.4 powered from DVCC (OFF after BOR) with LCD segment output S23."+ },+ {+ "number": "70",+ "name": "P5.5/S22",+ "type": "bidirectional",+ "description": "Digital I/O P5.5 powered from DVCC (OFF after BOR) with LCD segment output S22."+ },+ {+ "number": "71",+ "name": "P5.6/S21",+ "type": "bidirectional",+ "description": "Digital I/O P5.6 powered from DVCC (OFF after BOR) with LCD segment output S21."+ },+ {+ "number": "72",+ "name": "P5.7/S20",+ "type": "bidirectional",+ "description": "Digital I/O P5.7 powered from DVCC (OFF after BOR) with LCD segment output S20."+ },+ {+ "number": "73",+ "name": "P6.0/S19",+ "type": "bidirectional",+ "description": "Digital I/O P6.0 powered from DVCC (OFF after BOR) with LCD segment output S19."+ },+ {+ "number": "74",+ "name": "DVSYS",+ "type": "power_in",+ "description": "Digital power supply for I/Os; must be connected externally on board for proper device operation."+ },+ {+ "number": "75",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground supply."+ },+ {+ "number": "76",+ "name": "P6.1/S18",+ "type": "bidirectional",+ "description": "Digital I/O P6.1 powered from DVCC (OFF after BOR) with LCD segment output S18."+ },+ {+ "number": "77",+ "name": "P6.2/S17",+ "type": "bidirectional",+ "description": "Digital I/O P6.2 powered from DVCC (OFF after BOR) with LCD segment output S17."+ },+ {+ "number": "78",+ "name": "P6.3/S16",+ "type": "bidirectional",+ "description": "Digital I/O P6.3 powered from DVCC (OFF after BOR) with LCD segment output S16."+ },+ {+ "number": "79",+ "name": "P6.4/S15",+ "type": "bidirectional",+ "description": "Digital I/O P6.4 powered from DVCC (OFF after BOR) with LCD segment output S15."+ },+ {+ "number": "80",+ "name": "P6.5/S14",+ "type": "bidirectional",+ "description": "Digital I/O P6.5 powered from DVCC (OFF after BOR) with LCD segment output S14."+ },+ {+ "number": "81",+ "name": "P6.6/S13",+ "type": "bidirectional",+ "description": "Digital I/O P6.6 powered from DVCC (OFF after BOR) with LCD segment output S13."+ },+ {+ "number": "82",+ "name": "P6.7/S12",+ "type": "bidirectional",+ "description": "Digital I/O P6.7 powered from DVCC (OFF after BOR) with LCD segment output S12."+ },+ {+ "number": "83",+ "name": "P7.0/S11",+ "type": "bidirectional",+ "description": "Digital I/O P7.0 powered from DVCC (OFF after BOR) with LCD segment output S11."+ },+ {+ "number": "84",+ "name": "P7.1/S10",+ "type": "bidirectional",+ "description": "Digital I/O P7.1 powered from DVCC (OFF after BOR) with LCD segment output S10."+ },+ {+ "number": "85",+ "name": "P7.2/S9",+ "type": "bidirectional",+ "description": "Digital I/O P7.2 powered from DVCC (OFF after BOR) with LCD segment output S9."+ },+ {+ "number": "86",+ "name": "P7.3/S8",+ "type": "bidirectional",+ "description": "Digital I/O P7.3 powered from DVCC (OFF after BOR) with LCD segment output S8."+ },+ {+ "number": "87",+ "name": "P7.4/S7",+ "type": "bidirectional",+ "description": "Digital I/O P7.4 powered from DVCC (OFF after BOR) with LCD segment output S7."+ },+ {+ "number": "88",+ "name": "P7.5/S6",+ "type": "bidirectional",+ "description": "Digital I/O P7.5 powered from DVCC (OFF after BOR) with LCD segment output S6."+ },+ {+ "number": "89",+ "name": "P7.6/S5",+ "type": "bidirectional",+ "description": "Digital I/O P7.6 powered from DVCC (OFF after BOR) with LCD segment output S5."+ },+ {+ "number": "90",+ "name": "P7.7/S4",+ "type": "bidirectional",+ "description": "Digital I/O P7.7 powered from DVCC (OFF after BOR) with LCD segment output S4."+ },+ {+ "number": "91",+ "name": "P8.0/S3",+ "type": "bidirectional",+ "description": "Digital I/O P8.0 powered from DVCC (OFF after BOR) with LCD segment output S3."+ },+ {+ "number": "92",+ "name": "P8.1/S2",+ "type": "bidirectional",+ "description": "Digital I/O P8.1 powered from DVCC (OFF after BOR) with LCD segment output S2."+ },+ {+ "number": "93",+ "name": "P8.2/S1",+ "type": "bidirectional",+ "description": "Digital I/O P8.2 powered from DVCC (OFF after BOR) with LCD segment output S1."+ },+ {+ "number": "94",+ "name": "P8.3/S0",+ "type": "bidirectional",+ "description": "Digital I/O P8.3 powered from DVCC (OFF after BOR) with LCD segment output S0."+ },+ {+ "number": "95",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that selects digital I/O on the JTAG pins; it always has an internal pulldown enabled and doubles as Spy-Bi-Wire input clock SBWTCK."+ },+ {+ "number": "96",+ "name": "PJ.0/SMCLK/TDO",+ "type": "bidirectional",+ "description": "Port PJ.0 I/O (OFF after BOR); alternates are SMCLK clock output and JTAG test data output TDO."+ },+ {+ "number": "97",+ "name": "PJ.1/MCLK/TDI/TCLK",+ "type": "bidirectional",+ "description": "Port PJ.1 I/O (OFF after BOR); alternates are MCLK clock output and JTAG test data input TDI / test clock input TCLK."+ },+ {+ "number": "98",+ "name": "PJ.2/ADC10CLK/TMS",+ "type": "bidirectional",+ "description": "Port PJ.2 I/O (OFF after BOR); alternates are ADC10_A clock output and JTAG test mode select input TMS."+ },+ {+ "number": "99",+ "name": "PJ.3/ACLK/TCK",+ "type": "bidirectional",+ "description": "Port PJ.3 I/O (OFF after BOR); alternates are ACLK clock output and JTAG test clock input TCK."+ },+ {+ "number": "100",+ "name": "RST/NMI/SBWTDIO",+ "type": "input",+ "description": "Reset input active low with internal pullup enabled by default; alternates are nonmaskable interrupt input NMI and Spy-Bi-Wire data I/O SBWTDIO."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: MSP430F6723A is in the MSP430F672xA family. Per Table 4-1, pins 5 and 6 are NC (SD2P0/SD2N0 exist on; Table 4-3 lists VREF as signal type I, while Table 4-5 lists VREF (pin 7) as signal type O. Reported; RST/NMI/SBWTDIO is multi-function. Typed as input from the default RST function (Table 4-3 lists it "+ ],+ "pages_sent": 91,+ "cost_usd": 0.6891,+ "at": "2026-10-08T15:03:16"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430f6720a",+ "pages": 168,+ "sha256": "9f50329e4202500f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 100,+ "described": 100,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430f6723aipzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "51720097260ffba41c3062f85f67623721102fa535901c47cb555a1f444feeb3",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430f6723aipzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "04873d126f0bbc2515be6aa7178ab5f49f6d36b21b059a4de24983823b829014",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}