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MSP430F5509IRGZR
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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# MSP430F5509IRGZR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)++MSP430F5509IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P6.0/CB0/A0 | bidirectional | General-purpose digital I/O with Comparator_B input CB0 and ADC analog input A0. |+| 2 | P6.1/CB1/A1 | bidirectional | General-purpose digital I/O with Comparator_B input CB1 and ADC analog input A1. |+| 3 | P6.2/CB2/A2 | bidirectional | General-purpose digital I/O with Comparator_B input CB2 and ADC analog input A2. |+| 4 | P6.3/CB3/A3 | bidirectional | General-purpose digital I/O with Comparator_B input CB3 and ADC analog input A3. |+| 5 | P5.0/A8/VeREF+ | bidirectional | General-purpose digital I/O with ADC analog input A8 and external ADC reference input VeREF+. |+| 6 | P5.1/A9/VeREF- | bidirectional | General-purpose digital I/O with ADC analog input A9 and negative terminal VeREF- for an externally provided ADC reference. |+| 7 | AVCC1 | power_in | Analog power supply. |+| 8 | P5.4/XIN | bidirectional | General-purpose digital I/O; input terminal for crystal oscillator XT1. |+| 9 | P5.5/XOUT | bidirectional | General-purpose digital I/O; output terminal of crystal oscillator XT1. |+| 10 | AVSS1 | power_in | Analog ground supply. |+| 11 | DVCC1 | power_in | Digital power supply. |+| 12 | DVSS1 | power_in | Digital ground supply. |+| 13 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and it should only be connected to the recommended capacitor CVCORE. |+| 14 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt; TA0 clock input TA0CLK or ACLK output (divided by 1, 2, 4, 8, 16, or 32). |+| 15 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR0 capture input or compare output, and BSL transmit output. |+| 16 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR1 capture input or compare output, and BSL receive input. |+| 17 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR2 capture input or compare output. |+| 18 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR3 capture input or compare output. |+| 19 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR4 capture input or compare output. |+| 20 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt; TA1 clock input TA1CLK or Comparator_B output CBOUT. |+| 21 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt; TA1 CCR0 capture input or compare output. |+| 22 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt; TA1 CCR1 capture input or compare output. |+| 23 | PJ.0/TDO | bidirectional | General-purpose digital I/O; JTAG test data output port (TDO). |+| 24 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O; JTAG test data input (TDI) and test clock input (TCLK). |+| 25 | PJ.2/TMS | bidirectional | General-purpose digital I/O; JTAG test mode select (TMS). |+| 26 | PJ.3/TCK | bidirectional | General-purpose digital I/O; JTAG test clock (TCK). |+| 27 | DVSS2 | power_in | Digital ground supply. |+| 28 | DVCC2 | power_in | Digital power supply. |+| 29 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output. |+| 30 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data. |+| 31 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock. |+| 32 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 clock input/output or USCI_A1 SPI slave transmit enable. |+| 33 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out. |+| 34 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in. |+| 35 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |+| 36 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |+| 37 | VSSU | power_in | USB PHY ground supply. |+| 38 | PU.0/DP | bidirectional | General-purpose digital I/O controlled by the USB control register, or USB data terminal DP. |+| 39 | PUR | bidirectional | USB pullup resistor pin (open drain); its voltage level invokes the default USB BSL, and a 1-MΩ resistor to ground is recommended. |+| 40 | PU.1/DM | bidirectional | General-purpose digital I/O controlled by the USB control register, or USB data terminal DM. |+| 41 | VBUS | power_in | USB LDO input; connect to USB power source. |+| 42 | VUSB | power_out | USB LDO output. |+| 43 | V18 | power_out | USB regulated power for internal use only; no external current loading is possible. |+| 44 | AVSS2 | power_in | Analog ground supply. |+| 45 | P5.2/XT2IN | bidirectional | General-purpose digital I/O; input terminal for crystal oscillator XT2. |+| 46 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O; output terminal of crystal oscillator XT2. |+| 47 | TEST/SBWTCK | input | Test mode pin that selects digital I/O on the JTAG pins; also the Spy-Bi-Wire input clock. |+| 48 | RST/NMI/SBWTDIO | bidirectional | Reset input, active low (internal pullup enabled by default when configured as reset); also nonmaskable interrupt input and Spy-Bi-Wire data input/output. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `MSP430F5509IRGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `msp430f5509irgzr-etched.step` / `msp430f5509irgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5509irgzr.step` / `msp430f5509irgzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f5508) (134 pp, sha256 `39e075da0f1e3944`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430f5509irgzr-datasheet.pdf)
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input terminal for crystal oscillator XT1."+ },+ {+ "number": "9",+ "name": "P5.5/XOUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; output terminal of crystal oscillator XT1."+ },+ {+ "number": "10",+ "name": "AVSS1",+ "type": "power_in",+ "description": "Analog ground supply."+ },+ {+ "number": "11",+ "name": "DVCC1",+ "type": "power_in",+ "description": "Digital power supply."+ },+ {+ "number": "12",+ "name": "DVSS1",+ "type": "power_in",+ "description": "Digital ground supply."+ },+ {+ "number": "13",+ "name": "VCORE",+ "type": "power_out",+ "description": "Regulated core power supply output for internal use only; no external current loading is possible and it should only be connected to the recommended capacitor CVCORE."+ },+ {+ "number": "14",+ "name": "P1.0/TA0CLK/ACLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA0 clock input TA0CLK or ACLK output (divided by 1, 2, 4, 8, 16, or 32)."+ },+ {+ "number": "15",+ "name": "P1.1/TA0.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA0 CCR0 capture input or compare output, and BSL transmit output."+ },+ {+ "number": "16",+ "name": "P1.2/TA0.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA0 CCR1 capture input or compare output, and BSL receive input."+ },+ {+ "number": "17",+ "name": "P1.3/TA0.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA0 CCR2 capture input or compare output."+ },+ {+ "number": "18",+ "name": "P1.4/TA0.3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA0 CCR3 capture input or compare output."+ },+ {+ "number": "19",+ "name": "P1.5/TA0.4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA0 CCR4 capture input or compare output."+ },+ {+ "number": "20",+ "name": "P1.6/TA1CLK/CBOUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA1 clock input TA1CLK or Comparator_B output CBOUT."+ },+ {+ "number": "21",+ "name": "P1.7/TA1.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA1 CCR0 capture input or compare output."+ },+ {+ "number": "22",+ "name": "P2.0/TA1.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt; TA1 CCR1 capture input or compare output."+ },+ {+ "number": "23",+ "name": "PJ.0/TDO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; JTAG test data output port (TDO)."+ },+ {+ "number": "24",+ "name": "PJ.1/TDI/TCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; JTAG test data input (TDI) and test clock input (TCLK)."+ },+ {+ "number": "25",+ "name": "PJ.2/TMS",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; JTAG test mode select (TMS)."+ },+ {+ "number": "26",+ "name": "PJ.3/TCK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; JTAG test clock (TCK)."+ },+ {+ "number": "27",+ "name": "DVSS2",+ "type": "power_in",+ "description": "Digital ground supply."+ },+ {+ "number": "28",+ "name": "DVCC2",+ "type": "power_in",+ "description": "Digital power supply."+ },+ {+ "number": "29",+ "name": "P4.0/PM_UCB1STE/PM_UCA1CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output."+ },+ {+ "number": "30",+ "name": "P4.1/PM_UCB1SIMO/PM_UCB1SDA",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data."+ },+ {+ "number": "31",+ "name": "P4.2/PM_UCB1SOMI/PM_UCB1SCL",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock."+ },+ {+ "number": "32",+ "name": "P4.3/PM_UCB1CLK/PM_UCA1STE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 clock input/output or USCI_A1 SPI slave transmit enable."+ },+ {+ "number": "33",+ "name": "P4.4/PM_UCA1TXD/PM_UCA1SIMO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out."+ },+ {+ "number": "34",+ "name": "P4.5/PM_UCA1RXD/PM_UCA1SOMI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in."+ },+ {+ "number": "35",+ "name": "P4.6/PM_NONE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function."+ },+ {+ "number": "36",+ "name": "P4.7/PM_NONE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function."+ },+ {+ "number": "37",+ "name": "VSSU",+ "type": "power_in",+ "description": "USB PHY ground supply."+ },+ {+ "number": "38",+ "name": "PU.0/DP",+ "type": "bidirectional",+ "description": "General-purpose digital I/O controlled by the USB control register, or USB data terminal DP."+ },+ {+ "number": "39",+ "name": "PUR",+ "type": "bidirectional",+ "description": "USB pullup resistor pin (open drain); its voltage level invokes the default USB BSL, and a 1-MΩ resistor to ground is recommended."+ },+ {+ "number": "40",+ "name": "PU.1/DM",+ "type": "bidirectional",+ "description": "General-purpose digital I/O controlled by the USB control register, or USB data terminal DM."+ },+ {+ "number": "41",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB LDO input; connect to USB power source."+ },+ {+ "number": "42",+ "name": "VUSB",+ "type": "power_out",+ "description": "USB LDO output."+ },+ {+ "number": "43",+ "name": "V18",+ "type": "power_out",+ "description": "USB regulated power for internal use only; no external current loading is possible."+ },+ {+ "number": "44",+ "name": "AVSS2",+ "type": "power_in",+ "description": "Analog ground supply."+ },+ {+ "number": "45",+ "name": "P5.2/XT2IN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; input terminal for crystal oscillator XT2."+ },+ {+ "number": "46",+ "name": "P5.3/XT2OUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; output terminal of crystal oscillator XT2."+ },+ {+ "number": "47",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that selects digital I/O on the JTAG pins; also the Spy-Bi-Wire input clock."+ },+ {+ "number": "48",+ "name": "RST/NMI/SBWTDIO",+ "type": "bidirectional",+ "description": "Reset input, active low (internal pullup enabled by default when configured as reset); also nonmaskable interrupt input and Spy-Bi-Wire data input/output."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Exposed QFN thermal pad (Pad) is not a numbered pin and is omitted from the pins array. The datashee; Absolute maximum and recommended operating voltage/current limits are in Section 5 (pages 19-20), wh; Pin types for VCORE, VUSB, and V18 (power_out) and VBUS (power_in) are inferred from the Table 4-1 f",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 53,+ "cost_usd": 0.3329,+ "at": "2026-10-08T16:31:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430f5508",+ "pages": 134,+ "sha256": "39e075da0f1e3944",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430f5509irgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430f5509irgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b09b6101e8e7c8f30c4e0619d8e9aff1c4b645234530e6fd1914894ef7235e61",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}