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MSP430F5255IRGCR
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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+102@@ -0,0 +1,102 @@+# MSP430F5255IRGCR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-64-EP(9x9)++MSP430F5255IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P6.0/TA2CLK/SMCLK/CB0/A0 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 clock input, SMCLK output, Comparator_B input CB0 and ADC analog input A0. |+| 2 | P6.1/TA2.0/CB1/A1 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 CCR0 capture/compare output, Comparator_B input CB1, ADC analog input A1 and BSL transmit output. |+| 3 | P6.2/TA2.1/CB2/A2 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 CCR1 capture/compare output, Comparator_B input CB2, ADC analog input A2 and BSL receive input. |+| 4 | P6.3/TA2.2/CB3/A3 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 CCR2 capture/compare output, Comparator_B input CB3 and ADC analog input A3. |+| 5 | P6.4/CB4/A4 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB4 and ADC analog input A4. |+| 6 | P6.5/CB5/A5 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB5 and ADC analog input A5. |+| 7 | P6.6/CB6/A6 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB6 and ADC analog input A6. |+| 8 | P6.7/CB7/A7 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB7 and ADC analog input A7. |+| 9 | P5.0/A8/VeREF+ | bidirectional | General-purpose I/O on the DVCC domain, also ADC analog input A8 and external ADC reference voltage input VeREF+ (not available on all device types). |+| 10 | P5.1/A9/VeREF- | bidirectional | General-purpose I/O on the DVCC domain, also ADC analog input A9 and negative terminal for an externally applied ADC reference voltage VeREF- (not available on all device types). |+| 11 | AVCC | power_in | Analog power supply. |+| 12 | P5.4/XIN | bidirectional | General-purpose I/O on the DVCC domain, also input terminal for crystal oscillator XT1 (in bypass mode XIN can take a digital waveform from DVSS to DVCC or DVSS to DVIO). |+| 13 | P5.5/XOUT | bidirectional | General-purpose I/O on the DVCC domain, also output terminal of crystal oscillator XT1. |+| 14 | AVSS | power_in | Analog ground supply. |+| 15 | DVCC | power_in | Digital power supply. |+| 16 | DVSS | power_in | Digital ground supply. |+| 17 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and only the recommended capacitor CVCORE should be connected. |+| 18 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 clock input and ACLK output (divided by 1, 2, 4, 8, 16 or 32). |+| 19 | P1.1/TA0.0 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR0 capture input CCI0A and compare output Out0. |+| 20 | P1.2/TA0.1 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR1 capture input CCI1A and compare output Out1. |+| 21 | P1.3/TA0.2 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR2 capture input CCI2A and compare output Out2. |+| 22 | P1.4/TA0.3 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR3 capture input CCI3A and compare output Out3. |+| 23 | P1.5/TA0.4 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR4 capture input CCI4A and compare output Out4. |+| 24 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 clock input and Comparator_B output. |+| 25 | P1.7/TA1.0 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR0 capture input CCI0A and compare output Out0. |+| 26 | P2.0/TA1.1 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR1 capture input CCI1A and compare output Out1. |+| 27 | P2.1/TA1.2 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR2 capture input CCI2A and compare output Out2. |+| 28 | P2.2/UCB3SIMO/UCB3SDA | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave-in/master-out or I2C data (USCI_B3). |+| 29 | P2.3/UCB3SOMI/UCB3SCL | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave-out/master-in or I2C clock (USCI_B3). |+| 30 | P2.4/UCB3CLK/UCA3STE | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI clock input (slave) or output (master) and USCI_A3 SPI slave transmit enable. |+| 31 | P2.5/UCB3STE/UCA3CLK | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave transmit enable and USCI_A3 SPI clock input (slave) or output (master). |+| 32 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also RTC clock output for calibration and DMA external trigger input. |+| 33 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave transmit enable and USCI_A0 SPI clock input (slave) or output (master). |+| 34 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave-in/master-out or I2C data. |+| 35 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave-out/master-in or I2C clock. |+| 36 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI clock input (slave) or output (master) and USCI_A0 SPI slave transmit enable. |+| 37 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A0 UART transmit data or SPI slave-in/master-out. |+| 38 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A0 UART receive data or SPI slave-out/master-in. |+| 39 | DVSS | power_in | Digital ground supply for the DVIO domain. |+| 40 | DVIO | power_in | Digital I/O power supply for the DVIO domain; the voltage on DVIO is not supervised or monitored. |+| 41 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output. |+| 42 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data. |+| 43 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock. |+| 44 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI clock or USCI_A1 SPI slave transmit enable. |+| 45 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out. |+| 46 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in. |+| 47 | P4.6/PM_UCA3TXD/PM_UCA3SIMO | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A3 UART transmit data or SPI slave-in/master-out. |+| 48 | P4.7/PM_UCA3RXD/PM_UCA3SOMI | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A3 UART receive data or SPI slave-out/master-in. |+| 49 | P7.0/UCA2TXD/UCA2SIMO | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A2 UART transmit data or SPI slave-in/master-out. |+| 50 | P7.1/UCA2RXD/UCA2SOMI | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A2 UART receive data or SPI slave-out/master-in. |+| 51 | P7.2/UCB2CLK/UCA2STE | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI clock input (slave) or output (master) and USCI_A2 SPI slave transmit enable. |+| 52 | P7.3/UCB2SIMO/UCB2SDA | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave-in/master-out or I2C data. |+| 53 | P7.4/UCB2SOMI/UCB2SCL | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave-out/master-in or I2C clock. |+| 54 | P7.5/UCB2STE/UCA2CLK | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave transmit enable and USCI_A2 SPI clock input (slave) or output (master). |+| 55 | BSLEN | input | BSL enable input on the DVIO domain with internal pulldown; used together with RST/NMI for the DVIO-domain bootloader entry sequence. |+| 56 | RST/NMI | input | Active-low reset input or nonmaskable interrupt input on the DVIO domain; when driven externally, input swing from DVSS to DVIO is required and the internal pullup is enabled by default when configured as reset. |+| 57 | P5.2/XT2IN | bidirectional | General-purpose I/O on the DVCC domain, also input terminal for crystal oscillator XT2 (in bypass mode it can take a digital waveform from DVSS to DVCC or DVSS to DVIO). |+| 58 | P5.3/XT2OUT | bidirectional | General-purpose I/O on the DVCC domain, also output terminal of crystal oscillator XT2. |+| 59 | TEST/SBWTCK | input | Test mode pin that selects four-wire JTAG operation on the DVCC domain, and Spy-Bi-Wire input clock when Spy-Bi-Wire is active. |+| 60 | PJ.0/TDO | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test data output port. |+| 61 | PJ.1/TDI/TCLK | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test data input or test clock input. |+| 62 | PJ.2/TMS | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test mode select. |+| 63 | PJ.3/TCK | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test clock. |+| 64 | RSTDVCC/SBWTDIO | bidirectional | Nonconfigurable active-low reset input on the DVCC domain with internal pullup to DVCC (external drive requires swing from DVSS to DVCC), also Spy-Bi-Wire data input/output. |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(9x9) |+| Category | Embedded Processors & Controllers |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `MSP430F5255IRGCR`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `msp430f5255irgcr-etched.step` / `msp430f5255irgcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5255irgcr.step` / `msp430f5255irgcr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f5257) (112 pp, sha256 `52c9555dc979ab2f`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430f5255irgcr-datasheet.pdf)
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no external current loading is possible and only the recommended capacitor CVCORE should be connected."+ },+ {+ "number": "18",+ "name": "P1.0/TA0CLK/ACLK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA0 clock input and ACLK output (divided by 1, 2, 4, 8, 16 or 32)."+ },+ {+ "number": "19",+ "name": "P1.1/TA0.0",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR0 capture input CCI0A and compare output Out0."+ },+ {+ "number": "20",+ "name": "P1.2/TA0.1",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR1 capture input CCI1A and compare output Out1."+ },+ {+ "number": "21",+ "name": "P1.3/TA0.2",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR2 capture input CCI2A and compare output Out2."+ },+ {+ "number": "22",+ "name": "P1.4/TA0.3",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR3 capture input CCI3A and compare output Out3."+ },+ {+ "number": "23",+ "name": "P1.5/TA0.4",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR4 capture input CCI4A and compare output Out4."+ },+ {+ "number": "24",+ "name": "P1.6/TA1CLK/CBOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA1 clock input and Comparator_B output."+ },+ {+ "number": "25",+ "name": "P1.7/TA1.0",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR0 capture input CCI0A and compare output Out0."+ },+ {+ "number": "26",+ "name": "P2.0/TA1.1",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR1 capture input CCI1A and compare output Out1."+ },+ {+ "number": "27",+ "name": "P2.1/TA1.2",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR2 capture input CCI2A and compare output Out2."+ },+ {+ "number": "28",+ "name": "P2.2/UCB3SIMO/UCB3SDA",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave-in/master-out or I2C data (USCI_B3)."+ },+ {+ "number": "29",+ "name": "P2.3/UCB3SOMI/UCB3SCL",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave-out/master-in or I2C clock (USCI_B3)."+ },+ {+ "number": "30",+ "name": "P2.4/UCB3CLK/UCA3STE",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI clock input (slave) or output (master) and USCI_A3 SPI slave transmit enable."+ },+ {+ "number": "31",+ "name": "P2.5/UCB3STE/UCA3CLK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave transmit enable and USCI_A3 SPI clock input (slave) or output (master)."+ },+ {+ "number": "32",+ "name": "P2.6/RTCCLK/DMAE0",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with port interrupt, also RTC clock output for calibration and DMA external trigger input."+ },+ {+ "number": "33",+ "name": "P2.7/UCB0STE/UCA0CLK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave transmit enable and USCI_A0 SPI clock input (slave) or output (master)."+ },+ {+ "number": "34",+ "name": "P3.0/UCB0SIMO/UCB0SDA",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave-in/master-out or I2C data."+ },+ {+ "number": "35",+ "name": "P3.1/UCB0SOMI/UCB0SCL",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave-out/master-in or I2C clock."+ },+ {+ "number": "36",+ "name": "P3.2/UCB0CLK/UCA0STE",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B0 SPI clock input (slave) or output (master) and USCI_A0 SPI slave transmit enable."+ },+ {+ "number": "37",+ "name": "P3.3/UCA0TXD/UCA0SIMO",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_A0 UART transmit data or SPI slave-in/master-out."+ },+ {+ "number": "38",+ "name": "P3.4/UCA0RXD/UCA0SOMI",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_A0 UART receive data or SPI slave-out/master-in."+ },+ {+ "number": "39",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground supply for the DVIO domain."+ },+ {+ "number": "40",+ "name": "DVIO",+ "type": "power_in",+ "description": "Digital I/O power supply for the DVIO domain; the voltage on DVIO is not supervised or monitored."+ },+ {+ "number": "41",+ "name": "P4.0/PM_UCB1STE/PM_UCA1CLK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output."+ },+ {+ "number": "42",+ "name": "P4.1/PM_UCB1SIMO/PM_UCB1SDA",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data."+ },+ {+ "number": "43",+ "name": "P4.2/PM_UCB1SOMI/PM_UCB1SCL",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock."+ },+ {+ "number": "44",+ "name": "P4.3/PM_UCB1CLK/PM_UCA1STE",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI clock or USCI_A1 SPI slave transmit enable."+ },+ {+ "number": "45",+ "name": "P4.4/PM_UCA1TXD/PM_UCA1SIMO",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out."+ },+ {+ "number": "46",+ "name": "P4.5/PM_UCA1RXD/PM_UCA1SOMI",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in."+ },+ {+ "number": "47",+ "name": "P4.6/PM_UCA3TXD/PM_UCA3SIMO",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A3 UART transmit data or SPI slave-in/master-out."+ },+ {+ "number": "48",+ "name": "P4.7/PM_UCA3RXD/PM_UCA3SOMI",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A3 UART receive data or SPI slave-out/master-in."+ },+ {+ "number": "49",+ "name": "P7.0/UCA2TXD/UCA2SIMO",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_A2 UART transmit data or SPI slave-in/master-out."+ },+ {+ "number": "50",+ "name": "P7.1/UCA2RXD/UCA2SOMI",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_A2 UART receive data or SPI slave-out/master-in."+ },+ {+ "number": "51",+ "name": "P7.2/UCB2CLK/UCA2STE",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B2 SPI clock input (slave) or output (master) and USCI_A2 SPI slave transmit enable."+ },+ {+ "number": "52",+ "name": "P7.3/UCB2SIMO/UCB2SDA",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave-in/master-out or I2C data."+ },+ {+ "number": "53",+ "name": "P7.4/UCB2SOMI/UCB2SCL",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave-out/master-in or I2C clock."+ },+ {+ "number": "54",+ "name": "P7.5/UCB2STE/UCA2CLK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave transmit enable and USCI_A2 SPI clock input (slave) or output (master)."+ },+ {+ "number": "55",+ "name": "BSLEN",+ "type": "input",+ "description": "BSL enable input on the DVIO domain with internal pulldown; used together with RST/NMI for the DVIO-domain bootloader entry sequence."+ },+ {+ "number": "56",+ "name": "RST/NMI",+ "type": "input",+ "description": "Active-low reset input or nonmaskable interrupt input on the DVIO domain; when driven externally, input swing from DVSS to DVIO is required and the internal pullup is enabled by default when configured as reset."+ },+ {+ "number": "57",+ "name": "P5.2/XT2IN",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVCC domain, also input terminal for crystal oscillator XT2 (in bypass mode it can take a digital waveform from DVSS to DVCC or DVSS to DVIO)."+ },+ {+ "number": "58",+ "name": "P5.3/XT2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVCC domain, also output terminal of crystal oscillator XT2."+ },+ {+ "number": "59",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that selects four-wire JTAG operation on the DVCC domain, and Spy-Bi-Wire input clock when Spy-Bi-Wire is active."+ },+ {+ "number": "60",+ "name": "PJ.0/TDO",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVCC domain, also JTAG test data output port."+ },+ {+ "number": "61",+ "name": "PJ.1/TDI/TCLK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVCC domain, also JTAG test data input or test clock input."+ },+ {+ "number": "62",+ "name": "PJ.2/TMS",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVCC domain, also JTAG test mode select."+ },+ {+ "number": "63",+ "name": "PJ.3/TCK",+ "type": "bidirectional",+ "description": "General-purpose I/O on the DVCC domain, also JTAG test clock."+ },+ {+ "number": "64",+ "name": "RSTDVCC/SBWTDIO",+ "type": "bidirectional",+ "description": "Nonconfigurable active-low reset input on the DVCC domain with internal pullup to DVCC (external drive requires swing from DVSS to DVCC), also Spy-Bi-Wire data input/output."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The QFN exposed thermal pad is listed in Table 7-1 as 'Pad' with no pin number (N/A). It is not a nu; Figure 7-1 places a 'Supplied by DVIO' legend near the top of the RGC drawing, but Table 7-1 lists p; Table 7-1 footnote (13) lists reserved C6, D4-D6, E3-E6, F3-F8, G3 for the 80-pin ZXH/ZQE package on",+ "exposed pad 65 added from the footprint"+ ],+ "pages_sent": 46,+ "cost_usd": 0.3096,+ "at": "2026-10-08T16:24:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430f5257",+ "pages": 112,+ "sha256": "52c9555dc979ab2f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430f5255irgcr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430f5255irgcr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a3d43ab182f670edb59e62ee31ae443adef32ca54be5b2e496fa19b07feeb258",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}