component
MSP430F5254IRGCR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+102@@ -0,0 +1,102 @@+# MSP430F5254IRGCR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-64-EP(9x9)++MSP430F5254IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P6.0/TA2CLK/SMCLK/CB0/A0 | bidirectional | General-purpose digital I/O with port interrupt, also TA2 clock input, SMCLK output, Comparator_B input CB0 and ADC analog input A0; supplied by DVCC. |+| 2 | P6.1/TA2.0/CB1/A1 | bidirectional | General-purpose digital I/O with port interrupt, also TA2 CCR0 capture/compare, Comparator_B input CB1, ADC input A1 and BSL transmit output; supplied by DVCC. |+| 3 | P6.2/TA2.1/CB2/A2 | bidirectional | General-purpose digital I/O with port interrupt, also TA2 CCR1 capture/compare, Comparator_B input CB2, ADC input A2 and BSL receive input; supplied by DVCC. |+| 4 | P6.3/TA2.2/CB3/A3 | bidirectional | General-purpose digital I/O with port interrupt, also TA2 CCR2 capture/compare, Comparator_B input CB3 and ADC input A3; supplied by DVCC. |+| 5 | P6.4/CB4/A4 | bidirectional | General-purpose digital I/O with port interrupt, also Comparator_B input CB4 and ADC input A4; supplied by DVCC. |+| 6 | P6.5/CB5/A5 | bidirectional | General-purpose digital I/O with port interrupt, also Comparator_B input CB5 and ADC input A5; supplied by DVCC. |+| 7 | P6.6/CB6/A6 | bidirectional | General-purpose digital I/O with port interrupt, also Comparator_B input CB6 and ADC input A6; supplied by DVCC. |+| 8 | P6.7/CB7/A7 | bidirectional | General-purpose digital I/O with port interrupt, also Comparator_B input CB7 and ADC input A7; supplied by DVCC. |+| 9 | P5.0/A8/VeREF+ | bidirectional | General-purpose digital I/O, also ADC analog input A8 and external ADC reference input VeREF+; supplied by DVCC. |+| 10 | P5.1/A9/VeREF- | bidirectional | General-purpose digital I/O, also ADC analog input A9 and negative terminal for an external ADC reference VeREF-; supplied by DVCC. |+| 11 | AVCC | power_in | Analog power supply; TI recommends AVCC and DVCC come from the same source, with at most 0.3 V difference during power-up and operation. |+| 12 | P5.4/XIN | bidirectional | General-purpose digital I/O, or input terminal for crystal oscillator XT1 (or digital bypass input); supplied by DVCC. |+| 13 | P5.5/XOUT | bidirectional | General-purpose digital I/O, or output terminal of crystal oscillator XT1; supplied by DVCC. |+| 14 | AVSS | power_in | Analog ground supply. |+| 15 | DVCC | power_in | Digital power supply for the DVCC domain; recommended operating range is 1.8 V to 3.6 V. |+| 16 | DVSS | power_in | Digital ground supply. |+| 17 | VCORE | power_out | Regulated core power supply output for internal use only; no external DC loading, connect only to the recommended 470 nF CVCORE capacitor. |+| 18 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt, also TA0 clock input and ACLK output divided by 1, 2, 4, 8, 16 or 32; supplied by DVIO. |+| 19 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt, also TA0 CCR0 capture input/compare output; supplied by DVIO. |+| 20 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt, also TA0 CCR1 capture input/compare output; supplied by DVIO. |+| 21 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt, also TA0 CCR2 capture input/compare output; supplied by DVIO. |+| 22 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt, also TA0 CCR3 capture input/compare output; supplied by DVIO. |+| 23 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt, also TA0 CCR4 capture input/compare output; supplied by DVIO. |+| 24 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt, also TA1 clock input and Comparator_B output; supplied by DVIO. |+| 25 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt, also TA1 CCR0 capture input/compare output; supplied by DVIO. |+| 26 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt, also TA1 CCR1 capture input/compare output; supplied by DVIO. |+| 27 | P2.1/TA1.2 | bidirectional | General-purpose digital I/O with port interrupt, also TA1 CCR2 capture input/compare output; supplied by DVIO. |+| 28 | P2.2/UCB3SIMO/UCB3SDA | bidirectional | General-purpose digital I/O with port interrupt, also USCI_B3 SPI slave-in/master-out or I2C data; supplied by DVIO. |+| 29 | P2.3/UCB3SOMI/UCB3SCL | bidirectional | General-purpose digital I/O with port interrupt, also USCI_B3 SPI slave-out/master-in or I2C clock; supplied by DVIO. |+| 30 | P2.4/UCB3CLK/UCA3STE | bidirectional | General-purpose digital I/O with port interrupt, also USCI_B3 SPI clock input/output and USCI_A3 SPI slave transmit enable; supplied by DVIO. |+| 31 | P2.5/UCB3STE/UCA3CLK | bidirectional | General-purpose digital I/O with port interrupt, also USCI_B3 SPI slave transmit enable and USCI_A3 SPI clock input/output; supplied by DVIO. |+| 32 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose digital I/O with port interrupt, also RTC clock output for calibration and DMA external trigger input; supplied by DVIO. |+| 33 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O, also USCI_B0 SPI slave transmit enable and USCI_A0 SPI clock input/output; supplied by DVIO. |+| 34 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O, also USCI_B0 SPI slave-in/master-out or I2C data; supplied by DVIO. |+| 35 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O, also USCI_B0 SPI slave-out/master-in or I2C clock; supplied by DVIO. |+| 36 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O, also USCI_B0 SPI clock input/output and USCI_A0 SPI slave transmit enable; supplied by DVIO. |+| 37 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O, also USCI_A0 UART transmit data or SPI slave-in/master-out; supplied by DVIO. |+| 38 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O, also USCI_A0 UART receive data or SPI slave-out/master-in; supplied by DVIO. |+| 39 | DVSS | power_in | Digital ground supply. |+| 40 | DVIO | power_in | Digital I/O power supply for the DVIO domain, 1.62 V to 1.98 V; the voltage on this pin is not supervised or monitored. |+| 41 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output; supplied by DVIO. |+| 42 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data; supplied by DVIO. |+| 43 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock; supplied by DVIO. |+| 44 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI clock input/output or USCI_A1 SPI slave transmit enable; supplied by DVIO. |+| 45 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out; supplied by DVIO. |+| 46 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in; supplied by DVIO. |+| 47 | P4.6/PM_UCA3TXD/PM_UCA3SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A3 UART transmit data or SPI slave-in/master-out; supplied by DVIO. |+| 48 | P4.7/PM_UCA3RXD/PM_UCA3SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A3 UART receive data or SPI slave-out/master-in; supplied by DVIO. |+| 49 | P7.0/UCA2TXD/UCA2SIMO | bidirectional | General-purpose digital I/O, also USCI_A2 UART transmit data or SPI slave-in/master-out; supplied by DVIO. |+| 50 | P7.1/UCA2RXD/UCA2SOMI | bidirectional | General-purpose digital I/O, also USCI_A2 UART receive data or SPI slave-out/master-in; supplied by DVIO. |+| 51 | P7.2/UCB2CLK/UCA2STE | bidirectional | General-purpose digital I/O, also USCI_B2 SPI clock input/output and USCI_A2 SPI slave transmit enable; supplied by DVIO. |+| 52 | P7.3/UCB2SIMO/UCB2SDA | bidirectional | General-purpose digital I/O, also USCI_B2 SPI slave-in/master-out or I2C data; supplied by DVIO. |+| 53 | P7.4/UCB2SOMI/UCB2SCL | bidirectional | General-purpose digital I/O, also USCI_B2 SPI slave-out/master-in or I2C clock; supplied by DVIO. |+| 54 | P7.5/UCB2STE/UCA2CLK | bidirectional | General-purpose digital I/O, also USCI_B2 SPI slave transmit enable and USCI_A2 SPI clock input/output; supplied by DVIO. |+| 55 | BSLEN | input | BSL enable input with internal pulldown, on the DVIO supply domain. |+| 56 | RST/NMI | input | Reset input active low or nonmaskable interrupt input, on the DVIO domain; when configured as reset the internal pullup is enabled by default and external drive must swing from DVSS to DVIO. |+| 57 | P5.2/XT2IN | bidirectional | General-purpose digital I/O, or input terminal for crystal oscillator XT2 (or digital bypass input); supplied by DVCC. |+| 58 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O, or output terminal of crystal oscillator XT2; supplied by DVCC. |+| 59 | TEST/SBWTCK | input | Test mode pin that selects 4-wire JTAG operation, and Spy-Bi-Wire clock input when Spy-Bi-Wire is active; supplied by DVCC. |+| 60 | PJ.0/TDO | bidirectional | General-purpose digital I/O, or JTAG test data output port; supplied by DVCC. |+| 61 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O, or JTAG test data input or test clock input; supplied by DVCC. |+| 62 | PJ.2/TMS | bidirectional | General-purpose digital I/O, or JTAG test mode select; supplied by DVCC. |+| 63 | PJ.3/TCK | bidirectional | General-purpose digital I/O, or JTAG test clock; supplied by DVCC. |+| 64 | RSTDVCC/SBWTDIO | bidirectional | Nonconfigurable reset input active low with internal pullup to DVCC (DVSS to DVCC swing), and Spy-Bi-Wire data input/output when Spy-Bi-Wire is active; must be used for SBW instead of RST/NMI. |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(9x9) |+| Category | Embedded Processors & Controllers |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `MSP430F5254IRGCR`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `msp430f5254irgcr-etched.step` / `msp430f5254irgcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5254irgcr.step` / `msp430f5254irgcr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f5257) (112 pp, sha256 `52c9555dc979ab2f`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430f5254irgcr-datasheet.pdf)
page.jsonadded+543@@ -0,0 +1,543 @@+{+ "slug": "msp430f5254irgcr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430f5254irgcr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430f5254irgcr.kicad_sym",+ "msp430f5254irgcr.kicad_mod",+ "msp430f5254irgcr.glb",+ "msp430f5254irgcr.step",+ "msp430f5254irgcr.lbr",+ "docs/hero.png",+ "docs/msp430f5254irgcr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430f5254irgcr-hero.glb",+ "msp430f5254irgcr-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430F5254IRGCR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-64-EP(9x9)",+ "pin_count": 65,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430f5257",+ "parts": {+ "symbol": "msp430f5254irgcr.kicad_sym",+ "footprint": "msp430f5254irgcr.kicad_mod",+ "model_3d": "msp430f5254irgcr-hero.glb",+ "model_3d_plain": "msp430f5254irgcr.glb",+ "model_3d_step": "msp430f5254irgcr-etched.step",+ "model_3d_step_plain": "msp430f5254irgcr.step",+ "lbr": "msp430f5254irgcr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2055098",+ "digikey": "MSP430F5254IRGCR-ND",+ "mouser": "595-MSP430F5254IRGCR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T14:57:26Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "MSP430F5254IRGCR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-MSP430F5254IRGCR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "P6.0/TA2CLK/SMCLK/CB0/A0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA2 clock input, SMCLK output, Comparator_B input CB0 and ADC analog input A0; supplied by DVCC."+ },+ {+ "number": "2",+ "name": "P6.1/TA2.0/CB1/A1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA2 CCR0 capture/compare, Comparator_B input CB1, ADC input A1 and BSL transmit output; supplied by DVCC."+ },+ {+ "number": "3",+ "name": "P6.2/TA2.1/CB2/A2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA2 CCR1 capture/compare, Comparator_B input CB2, ADC input A2 and BSL receive input; supplied by DVCC."+ },+ {+ "number": "4",+ "name": "P6.3/TA2.2/CB3/A3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA2 CCR2 capture/compare, Comparator_B input CB3 and ADC input A3; supplied by DVCC."+ },+ {+ "number": "5",+ "name": "P6.4/CB4/A4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also Comparator_B input CB4 and ADC input A4; supplied by DVCC."+ },+ {+ "number": "6",+ "name": "P6.5/CB5/A5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also Comparator_B input CB5 and ADC input A5; supplied by DVCC."+ },+ {+ "number": "7",+ "name": "P6.6/CB6/A6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also Comparator_B input CB6 and ADC input A6; supplied by DVCC."+ },+ {+ "number": "8",+ "name": "P6.7/CB7/A7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also Comparator_B input CB7 and ADC input A7; supplied by DVCC."+ },+ {+ "number": "9",+ "name": "P5.0/A8/VeREF+",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also ADC analog input A8 and external ADC reference input VeREF+; supplied by DVCC."+ },+ {+ "number": "10",+ "name": "P5.1/A9/VeREF-",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also ADC analog input A9 and negative terminal for an external ADC reference VeREF-; supplied by DVCC."+ },+ {+ "number": "11",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog power supply; TI recommends AVCC and DVCC come from the same source, with at most 0.3 V difference during power-up and operation."+ },+ {+ "number": "12",+ "name": "P5.4/XIN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or input terminal for crystal oscillator XT1 (or digital bypass input); supplied by DVCC."+ },+ {+ "number": "13",+ "name": "P5.5/XOUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or output terminal of crystal oscillator XT1; supplied by DVCC."+ },+ {+ "number": "14",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground supply."+ },+ {+ "number": "15",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital power supply for the DVCC domain; recommended operating range is 1.8 V to 3.6 V."+ },+ {+ "number": "16",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground supply."+ },+ {+ "number": "17",+ "name": "VCORE",+ "type": "power_out",+ "description": "Regulated core power supply output for internal use only; no external DC loading, connect only to the recommended 470 nF CVCORE capacitor."+ },+ {+ "number": "18",+ "name": "P1.0/TA0CLK/ACLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA0 clock input and ACLK output divided by 1, 2, 4, 8, 16 or 32; supplied by DVIO."+ },+ {+ "number": "19",+ "name": "P1.1/TA0.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA0 CCR0 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "20",+ "name": "P1.2/TA0.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA0 CCR1 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "21",+ "name": "P1.3/TA0.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA0 CCR2 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "22",+ "name": "P1.4/TA0.3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA0 CCR3 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "23",+ "name": "P1.5/TA0.4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA0 CCR4 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "24",+ "name": "P1.6/TA1CLK/CBOUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA1 clock input and Comparator_B output; supplied by DVIO."+ },+ {+ "number": "25",+ "name": "P1.7/TA1.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA1 CCR0 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "26",+ "name": "P2.0/TA1.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA1 CCR1 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "27",+ "name": "P2.1/TA1.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also TA1 CCR2 capture input/compare output; supplied by DVIO."+ },+ {+ "number": "28",+ "name": "P2.2/UCB3SIMO/UCB3SDA",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also USCI_B3 SPI slave-in/master-out or I2C data; supplied by DVIO."+ },+ {+ "number": "29",+ "name": "P2.3/UCB3SOMI/UCB3SCL",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also USCI_B3 SPI slave-out/master-in or I2C clock; supplied by DVIO."+ },+ {+ "number": "30",+ "name": "P2.4/UCB3CLK/UCA3STE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also USCI_B3 SPI clock input/output and USCI_A3 SPI slave transmit enable; supplied by DVIO."+ },+ {+ "number": "31",+ "name": "P2.5/UCB3STE/UCA3CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also USCI_B3 SPI slave transmit enable and USCI_A3 SPI clock input/output; supplied by DVIO."+ },+ {+ "number": "32",+ "name": "P2.6/RTCCLK/DMAE0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt, also RTC clock output for calibration and DMA external trigger input; supplied by DVIO."+ },+ {+ "number": "33",+ "name": "P2.7/UCB0STE/UCA0CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B0 SPI slave transmit enable and USCI_A0 SPI clock input/output; supplied by DVIO."+ },+ {+ "number": "34",+ "name": "P3.0/UCB0SIMO/UCB0SDA",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B0 SPI slave-in/master-out or I2C data; supplied by DVIO."+ },+ {+ "number": "35",+ "name": "P3.1/UCB0SOMI/UCB0SCL",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B0 SPI slave-out/master-in or I2C clock; supplied by DVIO."+ },+ {+ "number": "36",+ "name": "P3.2/UCB0CLK/UCA0STE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B0 SPI clock input/output and USCI_A0 SPI slave transmit enable; supplied by DVIO."+ },+ {+ "number": "37",+ "name": "P3.3/UCA0TXD/UCA0SIMO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_A0 UART transmit data or SPI slave-in/master-out; supplied by DVIO."+ },+ {+ "number": "38",+ "name": "P3.4/UCA0RXD/UCA0SOMI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_A0 UART receive data or SPI slave-out/master-in; supplied by DVIO."+ },+ {+ "number": "39",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground supply."+ },+ {+ "number": "40",+ "name": "DVIO",+ "type": "power_in",+ "description": "Digital I/O power supply for the DVIO domain, 1.62 V to 1.98 V; the voltage on this pin is not supervised or monitored."+ },+ {+ "number": "41",+ "name": "P4.0/PM_UCB1STE/PM_UCA1CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output; supplied by DVIO."+ },+ {+ "number": "42",+ "name": "P4.1/PM_UCB1SIMO/PM_UCB1SDA",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data; supplied by DVIO."+ },+ {+ "number": "43",+ "name": "P4.2/PM_UCB1SOMI/PM_UCB1SCL",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock; supplied by DVIO."+ },+ {+ "number": "44",+ "name": "P4.3/PM_UCB1CLK/PM_UCA1STE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI clock input/output or USCI_A1 SPI slave transmit enable; supplied by DVIO."+ },+ {+ "number": "45",+ "name": "P4.4/PM_UCA1TXD/PM_UCA1SIMO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out; supplied by DVIO."+ },+ {+ "number": "46",+ "name": "P4.5/PM_UCA1RXD/PM_UCA1SOMI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in; supplied by DVIO."+ },+ {+ "number": "47",+ "name": "P4.6/PM_UCA3TXD/PM_UCA3SIMO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A3 UART transmit data or SPI slave-in/master-out; supplied by DVIO."+ },+ {+ "number": "48",+ "name": "P4.7/PM_UCA3RXD/PM_UCA3SOMI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A3 UART receive data or SPI slave-out/master-in; supplied by DVIO."+ },+ {+ "number": "49",+ "name": "P7.0/UCA2TXD/UCA2SIMO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_A2 UART transmit data or SPI slave-in/master-out; supplied by DVIO."+ },+ {+ "number": "50",+ "name": "P7.1/UCA2RXD/UCA2SOMI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_A2 UART receive data or SPI slave-out/master-in; supplied by DVIO."+ },+ {+ "number": "51",+ "name": "P7.2/UCB2CLK/UCA2STE",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B2 SPI clock input/output and USCI_A2 SPI slave transmit enable; supplied by DVIO."+ },+ {+ "number": "52",+ "name": "P7.3/UCB2SIMO/UCB2SDA",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B2 SPI slave-in/master-out or I2C data; supplied by DVIO."+ },+ {+ "number": "53",+ "name": "P7.4/UCB2SOMI/UCB2SCL",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B2 SPI slave-out/master-in or I2C clock; supplied by DVIO."+ },+ {+ "number": "54",+ "name": "P7.5/UCB2STE/UCA2CLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, also USCI_B2 SPI slave transmit enable and USCI_A2 SPI clock input/output; supplied by DVIO."+ },+ {+ "number": "55",+ "name": "BSLEN",+ "type": "input",+ "description": "BSL enable input with internal pulldown, on the DVIO supply domain."+ },+ {+ "number": "56",+ "name": "RST/NMI",+ "type": "input",+ "description": "Reset input active low or nonmaskable interrupt input, on the DVIO domain; when configured as reset the internal pullup is enabled by default and external drive must swing from DVSS to DVIO."+ },+ {+ "number": "57",+ "name": "P5.2/XT2IN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or input terminal for crystal oscillator XT2 (or digital bypass input); supplied by DVCC."+ },+ {+ "number": "58",+ "name": "P5.3/XT2OUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or output terminal of crystal oscillator XT2; supplied by DVCC."+ },+ {+ "number": "59",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that selects 4-wire JTAG operation, and Spy-Bi-Wire clock input when Spy-Bi-Wire is active; supplied by DVCC."+ },+ {+ "number": "60",+ "name": "PJ.0/TDO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or JTAG test data output port; supplied by DVCC."+ },+ {+ "number": "61",+ "name": "PJ.1/TDI/TCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or JTAG test data input or test clock input; supplied by DVCC."+ },+ {+ "number": "62",+ "name": "PJ.2/TMS",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or JTAG test mode select; supplied by DVCC."+ },+ {+ "number": "63",+ "name": "PJ.3/TCK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O, or JTAG test clock; supplied by DVCC."+ },+ {+ "number": "64",+ "name": "RSTDVCC/SBWTDIO",+ "type": "bidirectional",+ "description": "Nonconfigurable reset input active low with internal pullup to DVCC (DVSS to DVCC swing), and Spy-Bi-Wire data input/output when Spy-Bi-Wire is active; must be used for SBW instead of RST/NMI."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The QFN exposed pad has no numbered terminal in the datasheet; it is listed as 'PAD' and typed power; Datasheet pin-function table (Table 9-56) labels P6.3 as TA2.1, but Table 7-1 and the pin diagram la; Pin 39 (DVSS) and pin 40 (DVIO) are the DVIO domain supply pins, and the datasheet gives the DVIO ra",+ "exposed pad 65 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 46,+ "cost_usd": 0.3089,+ "at": "2026-10-08T14:57:04"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430f5257",+ "pages": 112,+ "sha256": "52c9555dc979ab2f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430f5254irgcr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430f5254irgcr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "2ae80c2dbeb6f3ffc0641f3f5c5fb39d1f358b59a3c2aaefa80b99ae40ae59f0",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}