MP3924GU-Z

@@ -0,0 +1,73 @@+# MP3924GU-Z++**Monolithic Power Systems** · Power Over Ethernet (PoE) Controllers · QFN-32(5x5)++MP3924GU-Z from Monolithic Power Systems, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GATE1 | output | MOSFET gate driver for port 1. Drives the external pass N-MOSFET for port 1. Float if not used. |+| 2 | OUT1 | input | Output voltage sense pin for port 1. Connect to the output interface return for detection, classification, voltage sensing, and current-limit foldback control. Float if not used. |+| 3 | INT2 | output | High-priority interrupt request pin. Open-drain output that pulls low when the selected high-priority interrupt source register is set and the interrupt is enabled. Tie to DGND if unused. Max sink 20mA (5mA recommended). |+| 4 | SGND1 | input | Current-sense negative input for port 1 and port 2. Connect to the low-side terminal of the sense resistor with a Kelvin connection. Tie to DGND if unused. |+| 5 | CLS5 | input | Class 5 enable input. Internally pulled down to DGND via 50kΩ. Leave floating to disable Class 5 classification (802.3at-compliant); tie to VCC to enable Class 5 devices. Status latched at start-up/reset. |+| 6 | AUTO | input | Automatic mode setting pin. Internally pulled up to VCC via 50kΩ. Float for automatic mode (default), tie to DGND for default shutdown mode. Status latched at start-up/reset. |+| 7 | MID | input | Midspan mode setting pin. Internally pulled up to VCC via 50kΩ. Float for midspan mode (re-initiate detection every 2.8s), tie to DGND to disable midspan mode. Status latched at start-up/reset. |+| 8 | INT1 | output | Interrupt request pin for all interrupt source events. Open-drain output; pulls low when the interrupt register is set and interrupts are enabled. Tie to DGND if unused. Max sink 20mA (5mA recommended). |+| 9 | SCL | input | I2C clock input pin. Requires external pull-up (typically 4.7kΩ) to VCC. Tie to VCC if I2C interface is not used. |+| 10 | SDAO | output | I2C serial data output pin (open-drain). Requires external pull-up (typically 4.7kΩ) to VCC. Connect SDAO to SDAI for non-isolated applications. Tie to DGND if I2C unused. Max sink 20mA. |+| 11 | SDAI | input | I2C serial data input pin. Requires external pull-up (typically 4.7kΩ) to VCC. Connect SDAI to SDAO for non-isolated applications. Tie to DGND if I2C unused. |+| 12 | EN | input | Enable input. Turns all internal circuits and four ports (except the VCC regulator) on/off. Tie EN to VCC to enable the device automatically. VHI ≥ 2.5V, VLI ≤ 0.4V. |+| 13 | A0 | input | I2C address setting pin (LSB). Tie to VCC or DGND to set the lower 4 address bits (address = 010 A3 A2 A1 A0). Latched at start-up/reset. Internally pulled up to VCC via 50kΩ. |+| 14 | A1 | input | I2C address setting pin. Tie to VCC or DGND to set the lower 4 address bits. Latched at start-up/reset. Internally pulled up to VCC via 50kΩ. |+| 15 | A2 | input | I2C address setting pin. Tie to VCC or DGND to set the lower 4 address bits. Latched at start-up/reset. Internally pulled up to VCC via 50kΩ. |+| 16 | A3 | input | I2C address setting pin (MSB of lower nibble). Tie to VCC or DGND to set the lower 4 address bits. Latched at start-up/reset. Internally pulled up to VCC via 50kΩ. |+| 17 | DGND | power_in | Ground of the internal digital and analog circuit. |+| 18 | SGND2 | input | Current-sense negative input for port 3 and port 4. Connect to the low-side terminal of the sense resistor with a Kelvin connection. Tie to DGND if unused. |+| 19 | PGND | power_in | Ground of the input power supply. |+| 20 | VCC | power_out | 3.3V internal regulator output for analog and digital circuit supply. Requires a minimum 1µF ceramic capacitor to DGND. Current limit ≈17mA. |+| 21 | PMAX | input | Maximum loading power setting pin. Connect a resistor from PMAX to DGND to set the total power capability across all four output ports. PMAX setting latched at start-up/reset. |+| 22 | VIN | power_in | Power supply input for both VCC regulator and output ports. Recommended operating range 44V to 57V (absolute max 80V). Bypass with at least 0.1µF/100V ceramic between VIN and PGND. |+| 23 | SENSE4 | input | Current-sense pin from the high-side sense resistor terminal for port 4. Recommended 0.25Ω sense resistor with Kelvin connection. Tie to DGND if unused. |+| 24 | GATE4 | output | MOSFET gate driver for port 4. Drives the external pass N-MOSFET for port 4. Float if not used. |+| 25 | OUT4 | input | Output voltage sense pin for port 4. Connect to the output interface return for detection, classification, voltage sensing, and current-limit foldback control. Float if unused. |+| 26 | SENSE3 | input | Current-sense pin from the high-side sense resistor terminal for port 3. Recommended 0.25Ω sense resistor with Kelvin connection. Tie to DGND if unused. |+| 27 | GATE3 | output | MOSFET gate driver for port 3. Drives the external pass N-MOSFET for port 3. Float if not used. |+| 28 | OUT3 | input | Output voltage sense pin for port 3. Connect to the output interface return for detection, classification, voltage sensing, and current-limit foldback control. Float if unused. |+| 29 | SENSE2 | input | Current-sense pin from the high-side sense resistor terminal for port 2. Recommended 0.25Ω sense resistor with Kelvin connection. Tie to DGND if unused. |+| 30 | GATE2 | output | MOSFET gate driver for port 2. Drives the external pass N-MOSFET for port 2. Float if not used. |+| 31 | OUT2 | input | Output voltage sense pin for port 2. Connect to the output interface return for detection, classification, voltage sensing, and current-limit foldback control. Float if unused. |+| 32 | SENSE1 | input | Current-sense pin from the high-side sense resistor terminal for port 1. Recommended 0.25Ω sense resistor with Kelvin connection. Tie to DGND if unused. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Monolithic Power Systems |+| Package | QFN-32(5x5) |+| Category | Power Management (PMIC) |+| Pins | 32 |++## Ordering variants++Same part, different packaging or reel option.++- `MP3924GU-Z`++## CAD (KiCad official)++- Symbol: `MP3924GU-Z`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Monolithic Power Systems datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589838151171665920) (56 pp, sha256 `e746f450cbdd2478`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mp3924gu-z-datasheet.pdf)

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