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MC74LVX4051DR2G
Public Made by Adomby adom
onsemi Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+108docs/hero.pngdocs/mc74lvx4051dr2g-datasheet.pdf+4855mc74lvx4051dr2g-etched.glbmc74lvx4051dr2g-hero.glbmc74lvx4051dr2g-hero.overlay.json+436mc74lvx4051dr2g.glbmc74lvx4051dr2g.kicad_mod+348mc74lvx4051dr2g.kicad_sym+77mc74lvx4051dr2g.lbr+154mc74lvx4051dr2g.step+5425package.json+243page.json+249viewers/footprint.html+1viewers/symbol.html+1README.mdadded+108@@ -0,0 +1,108 @@+# MC74LVX4051DR2G++**onsemi** · Signal Switches, Multiplexers, Decoders · SOIC-16++MC74LVX4051DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | X4 | passive | Analog input/output channel 4, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 2 | X6 | passive | Analog input/output channel 6, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 3 | X | passive | Common analog output/input that is connected to the selected channel X0 to X7; analog signal must stay between VEE and VCC. |+| 4 | X7 | passive | Analog input/output channel 7, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 5 | X5 | passive | Analog input/output channel 5, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 6 | Enable | input | Active-high enable: when HIGH all analog switches are turned off; input is overvoltage tolerant with VIN from 0 to 6.0 V and should be tied to VCC or GND. |+| 7 | VEE | power_in | Negative DC supply, recommended range −6.0 V to GND (VEE must not exceed GND); it sets the lower limit of the analog signal range. |+| 8 | GND | power_in | Ground reference for the digital control inputs and the supply voltages; all logic levels are referenced to GND. |+| 9 | C | input | Channel-select address input (most significant bit) that must be at VCC or GND logic levels with VIN from 0 to 6.0 V. |+| 10 | B | input | Channel-select address input (middle bit) that must be at VCC or GND logic levels with VIN from 0 to 6.0 V. |+| 11 | A | input | Channel-select address input (least significant bit) that must be at VCC or GND logic levels with VIN from 0 to 6.0 V. |+| 12 | X3 | passive | Analog input/output channel 3, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 13 | X0 | passive | Analog input/output channel 0, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 14 | X1 | passive | Analog input/output channel 1, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 15 | X2 | passive | Analog input/output channel 2, connected to the common X terminal when selected by A, B, C with Enable LOW; analog signal must stay between VEE and VCC. |+| 16 | VCC | power_in | Positive DC supply, recommended 2.5 V to 6.0 V referenced to GND and VCC − VEE of 2.5 V to 6.0 V; absolute maximum is 7.0 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Negative DC Supply Voltage (Referenced to GND) | VEE | -6 | | 0 | V | | 3 |+| Positive DC Supply Voltage (Referenced to GND) | VCC | 2.5 | | 6 | V | Referenced to GND | 3 |+| Positive DC Supply Voltage (Referenced to VEE) | VCC | 2.5 | | 6 | V | Referenced to VEE | 3 |+| Digital Input Voltage (Note 5) | VIN | 0 | | 6 | V | Referenced to GND; Note 5: unused inputs may not be left open | 3 |+| Operating Temperature Range, All Package Types | TA | -55 | | 125 | °C | | 3 |+| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 100 | ns/V | VCC = 3.0 V ±0.3 V | 3 |+| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 20 | ns/V | VCC = 5.0 V ±0.5 V | 3 |+| Negative DC Supply Voltage (Referenced to GND) | VEE | -7 | | 0.5 | V | | 3 |+| Positive DC Supply Voltage (Referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 3 |+| Positive DC Supply Voltage (Referenced to VEE) | VCC | -0.5 | | 7 | V | Referenced to VEE | 3 |+| Digital Input Voltage (Referenced to GND) | VIN | -0.5 | | 7 | V | Referenced to GND | 3 |+| DC Current, Into or Out of Any Pin | I | -50 | | 50 | mA | | 3 |+| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 3 |+| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 3 |+| Junction Temperature under Bias | TJ | | | 150 | °C | | 3 |+| ESD Withstand Voltage, Human Body Model | VESD | 2000 | | | V | Human Body Model, tested to EIA/JESD22-A114-A; printed as > 2000 | 3 |+| ESD Withstand Voltage, Machine Model | VESD | 200 | | | V | Machine Model, tested to EIA/JESD22-A115-A; printed as > 200 | 3 |+| ESD Withstand Voltage, Charged Device Model | VESD | 1000 | | | V | Charged Device Model, tested to JESD22-C101-A; printed as > 1000 | 3 |+| Latchup Performance | ILATCHUP | -300 | | 300 | mA | Above VCC and below GND at 125°C (EIA/JESD78) | 3 |+| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 1.9 | | | V | VCC = 2.5 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 2.1 | | | V | VCC = 3.0 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.15 | | | V | VCC = 4.5 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 4.2 | | | V | VCC = 6.0 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 0.6 | V | VCC = 2.5 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 0.9 | V | VCC = 3.0 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 1.35 | V | VCC = 4.5 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 1.8 | V | VCC = 6.0 V; guaranteed −55 to 125 °C (same limit in all three temperature columns) | 4 |+| Maximum Input Leakage Current, Channel-Select or Enable Inputs | IIN | -1 | | 1 | µA | VIN = 6.0 or GND, 0 V to 6.0 V; guaranteed −55 to 125 °C | 4 |+| Maximum Quiescent Supply Current (per Package) | ICC | | | 80 | µA | Channel Select, Enable and VIS = VCC or GND; VCC = 6.0 V; guaranteed −55 to 125 °C | 4 |+| Maximum ON Resistance | RON | | | 120 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; guaranteed −55 to 125 °C | 4 |+| Maximum ON Resistance | RON | | | 55 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; guaranteed −55 to 125 °C | 4 |+| Maximum ON Resistance | RON | | | 37 | Ω | VCC = 3.0 V, VEE = −3.0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; guaranteed −55 to 125 °C | 4 |+| Maximum Difference in ON Resistance Between Any Two Channels in the Same Package | RON | | | 20 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; guaranteed −55 to 125 °C | 4 |+| Maximum Difference in ON Resistance Between Any Two Channels in the Same Package | RON | | | 18 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; guaranteed −55 to 125 °C | 4 |+| Maximum Difference in ON Resistance Between Any Two Channels in the Same Package | RON | | | 15 | Ω | VCC = 3.0 V, VEE = −3.0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; guaranteed −55 to 125 °C | 4 |+| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 50 | ns | VCC = 2.5 V, VEE = 0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 35 | ns | VCC = 3.0 V, VEE = 0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 30 | ns | VCC = 4.5 V, VEE = 0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | | | 28 | ns | VCC = 3.0 V, VEE = −3.0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Enable to Analog Output | tPLZ, tPHZ | | | 50 | ns | VCC = 2.5 V, VEE = 0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Enable to Analog Output | tPLZ, tPHZ | | | 35 | ns | VCC = 3.0 V, VEE = 0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Enable to Analog Output | tPLZ, tPHZ | | | 30 | ns | VCC = 4.5 V, VEE = 0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Propagation Delay, Enable to Analog Output | tPLZ, tPHZ | | | 28 | ns | VCC = 3.0 V, VEE = −3.0 V; CL = 50 pF; guaranteed −55 to 125 °C | 5 |+| Maximum Input Capacitance, Channel-Select or Enable Inputs | CIN | | | 10 | pF | | 5 |+| Maximum Capacitance Analog I/O | CI/O | | | 10 | pF | All switches off | 5 |+| Maximum Capacitance Common O/I | CI/O | | | 10 | pF | All switches off | 5 |+| Maximum Capacitance Feedthrough | CI/O | | | 1 | pF | All switches off | 5 |+| Thermal Resistance, Junction-to-Ambient, SOIC | θJA | | 143 | | °C/W | | 3 |+| Power Dissipation in Still Air, SOIC | PD | | 500 | | mW | Still air | 3 |++## CAD (KiCad official)++- Symbol: `MC74LVX4051DR2G`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `mc74lvx4051dr2g-etched.step` / `mc74lvx4051dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74lvx4051dr2g.step` / `mc74lvx4051dr2g.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929216494637056) (16 pp, sha256 `d25ec412520763a2`, retrieved 2026-10-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mc74lvx4051dr2g-datasheet.pdf)
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The Channel-Select and Enable inputs are compatible with standard CMOS outputs. These inputs are overvoltage tolerant \(OVT\) for level translation from 6.0 V down to 3.0 V. This device has been designed so the ON resistance \(RON\) is more linear over input voltage than the RON of metal-gate CMOS analog switches and High-Speed CMOS analog switches.)+/Title (MC74LVX4051 - Analog Multiplexer/Demultiplexer)+>>+endobj+2 0 obj+<<+/Type /Pages+/Kids [6 0 R 7 0 R 8 0 R 9 0 R 10 0 R 11 0 R 12 0 R 13 0 R 14 0 R 15 0 R+16 0 R 17 0 R 18 0 R 19 0 R 20 0 R 21 0 R]+/Count 16+>>+endobj+3 0 obj+<<+/Length 4714+/Subtype /XML+/Type /Metadata+>>+stream +<?xpacket begin="" id="W5M0MpCehiHzreSzNTczkc9d"?>+<x:xmpmeta xmlns:x="adobe:ns:meta/" x:xmptk="Adobe XMP Core 5.6-c017 91.164464, 2020/06/15-10:20:05 ">+ <rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">+ <rdf:Description rdf:about=""+ xmlns:xmp="http://ns.adobe.com/xap/1.0/"+ xmlns:dc="http://purl.org/dc/elements/1.1/"+ xmlns:pdf="http://ns.adobe.com/pdf/1.3/"+ xmlns:xmpMM="http://ns.adobe.com/xap/1.0/mm/"+ xmlns:illustrator="http://ns.adobe.com/illustrator/1.0/">+ <xmp:CreatorTool>BroadVision, Inc.</xmp:CreatorTool>+ <xmp:ModifyDate>2020-09-16T12:12+02:00</xmp:ModifyDate>+ <xmp:CreateDate>2014-08-14T09:12:08+02:00</xmp:CreateDate>+ <xmp:MetadataDate>2020-09-16T12:12+02:00</xmp:MetadataDate>+ <dc:format>application/pdf</dc:format>+ <dc:title>+ <rdf:Alt>+ <rdf:li xml:lang="x-default">MC74LVX4051 - Analog Multiplexer/Demultiplexer</rdf:li>+ </rdf:Alt>+ </dc:title>+ <dc:creator>+ <rdf:Seq>+ <rdf:li>ON Semiconductor</rdf:li>+ </rdf:Seq>+ </dc:creator>+ <dc:description>+ <rdf:Alt>+ <rdf:li xml:lang="x-default">The MC74LVX4051 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low leakage currents. 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