MC74HC595ADTR2G

@@ -0,0 +1,60 @@+# MC74HC595ADTR2G++**onsemi** · Shifting Register · TSSOP-16++MC74HC595ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | tri_state | Parallel data output bit B from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE (pin 13) is LOW; drives up to 15 LSTTL loads. Output goes to high-impedance when OE is HIGH. |+| 2 | QC | tri_state | Parallel data output bit C from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 3 | QD | tri_state | Parallel data output bit D from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 4 | QE | tri_state | Parallel data output bit E from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 5 | QF | tri_state | Parallel data output bit F from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 6 | QG | tri_state | Parallel data output bit G from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 7 | QH | tri_state | Parallel data output bit H (MSB position) from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 8 | GND | power_in | Ground reference (0 V). Common return for supply and I/O. |+| 9 | SQH | output | Serial data output from the shift register (Q_H of the shift stage, not the latch). Used to cascade multiple MC74HC595A devices; connects to the A (serial data input) of the next stage. Not affected by OUTPUT ENABLE. |+| 10 | RESET | input | Asynchronous active-LOW reset for the shift register only. When LOW, all shift-register stages are cleared to 0; the storage latch is not affected until a LATCH CLOCK edge propagates the cleared data. |+| 11 | SHIFT_CLOCK | input | Shift-register clock input (SPI SCK equivalent). On the LOW-to-HIGH transition, serial data on A (pin 14) is clocked into stage QA and the shift register advances one bit toward SQH. f_max = 24-35 MHz at Vcc = 6 V. |+| 12 | LATCH_CLOCK | input | Storage latch (register) clock. On the LOW-to-HIGH transition, the current shift-register contents are transferred into the 8-bit output latch driving QA-QH. Typically the SPI /CS or 'RCLK' line. |+| 13 | OUTPUT_ENABLE | input | Active-LOW output enable for the parallel outputs QA-QH. LOW enables the 3-state drivers; HIGH forces QA-QH into high-impedance. Does not affect the shift register, latch contents, or SQH. |+| 14 | A | input | Serial data input to the shift register (SPI MOSI equivalent). Sampled on the rising edge of SHIFT CLOCK and loaded into stage QA. |+| 15 | QA | tri_state | Parallel data output bit A (LSB position) from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW. |+| 16 | VCC | power_in | Positive supply rail. Recommended operating range 2.0 V to 6.0 V (absolute max 7.0 V). Bypass with 0.1 uF close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `MC74HC595ADTR2GDTR2G`+- `MC74HC595ADTR2GDTR2`+- `MC74HC595ADTR2GDR2G`+- `MC74HC595ADTR2GDG`+- `MC74HC595ADTR2GMNR4G`+- `MC74HC595ADTR2GMN`++## CAD (KiCad official)++- Symbol: `MC74HC595ADTR2G`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc595adtr2-d.pdf) (13 pp, sha256 `77ce5ff50b90c4e5`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mc74hc595adtr2g-datasheet.pdf)

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