component
MC74HC4538ADR2G
Public Made by Adomby adom
onsemi Monostable Multivibrators, SOIC-16. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.
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README.md+116docs/hero.pngdocs/mc74hc4538adr2g-datasheet.pdf+4355mc74hc4538adr2g-etched.glbmc74hc4538adr2g-hero.glbmc74hc4538adr2g-hero.overlay.json+436mc74hc4538adr2g.glbmc74hc4538adr2g.kicad_mod+348mc74hc4538adr2g.kicad_sym+77mc74hc4538adr2g.lbr+154mc74hc4538adr2g.step+5425package.json+275page.json+281viewers/footprint.html+1viewers/symbol.html+1README.mdadded+116@@ -0,0 +1,116 @@+# MC74HC4538ADR2G++**onsemi** · Monostable Multivibrators · SOIC-16++MC74HC4538ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | External ground; the external timing capacitors discharge to ground through this pin, and it must be hard-wired to GND. |+| 2 | CX1/RX1 | passive | External timing component connection for multivibrator 1, tied to the common point of Rx and Cx; polystyrene capacitors are recommended and electrolytic capacitors are not recommended due to high leakage. |+| 3 | RESET 1 | input | Active-low reset input; a low level forces Q1 low and NQ1 high regardless of the output pulse circuitry. |+| 4 | A1 | input | Positive-edge trigger input for multivibrator 1, triggered by a rising edge when B1 is high. |+| 5 | B1 | input | Negative-edge trigger input for multivibrator 1, triggered by a falling edge when A1 is low. |+| 6 | Q1 | output | Noninverted monostable output 1, normally low, pulsing high when multivibrator 1 is triggered; pulse width set by Rx and Cx. |+| 7 | NQ1 | output | Inverted monostable output 1, normally high, pulsing low when multivibrator 1 is triggered. |+| 8 | GND | power_in | Ground connection, identified as GND (pin 8) on the logic diagram. |+| 9 | NQ2 | output | Inverted monostable output 2, normally high, pulsing low when multivibrator 2 is triggered. |+| 10 | Q2 | output | Noninverted monostable output 2, normally low, pulsing high when multivibrator 2 is triggered; pulse width set by Rx and Cx. |+| 11 | B2 | input | Negative-edge trigger input for multivibrator 2, triggered by a falling edge when A2 is low. |+| 12 | A2 | input | Positive-edge trigger input for multivibrator 2, triggered by a rising edge when B2 is high. |+| 13 | RESET 2 | input | Active-low reset input; a low level forces Q2 low and NQ2 high regardless of the output pulse circuitry. |+| 14 | CX2/RX2 | passive | External timing component connection for multivibrator 2, tied to the common point of Rx and Cx; polystyrene capacitors are recommended and electrolytic capacitors are not recommended due to high leakage. |+| 15 | GND | power_in | External ground; the external timing capacitors discharge to ground through this pin, and it must be hard-wired to GND. |+| 16 | VCC | power_in | Positive supply pin (pin 16 = VCC on the logic diagram); the datasheet specifies VCC of 2.0 V to 6.0 V referenced to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-16 |+| Category | Logic ICs |+| Pins | 16 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| DC Supply Voltage | VCC | -0.5 | | 7 | V | | 3 |+| DC Input Voltage | VI | -0.5 | | | V | Printed as −0.5 ≤ VI ≤ VCC + 0.5 | 3 |+| DC Output Voltage (Note 1) | VO | -0.5 | | | V | Printed as −0.5 ≤ VO ≤ VCC + 0.5 | 3 |+| DC Input Diode Current | IIK | -20 | | 20 | mA | A, B, Reset | 3 |+| DC Input Diode Current | IIK | -30 | | 30 | mA | CX, RX | 3 |+| DC Output Diode Current | IOK | -25 | | 25 | mA | | 3 |+| DC Output Sink Current | IO | -25 | | 25 | mA | | 3 |+| DC Supply Current per Supply Pin | ICC | -100 | | 100 | mA | Per supply pin | 3 |+| DC Ground Current per Ground Pin | IGND | -100 | | 100 | mA | Per ground pin | 3 |+| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 3 |+| Lead temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 3 |+| Junction temperature under bias | TJ | | | 150 | °C | Under bias | 3 |+| ESD Withstand Voltage, Human Body Model | VESD | 2000 | | | V | EIA/JESD22-A114-A; printed as > 2000 | 3 |+| ESD Withstand Voltage, Machine Model | VESD | 100 | | | V | EIA/JESD22-A115-A; printed as > 100 | 3 |+| ESD Withstand Voltage, Charged Device Model | VESD | 500 | | | V | JESD22-C101-A; printed as > 500 | 3 |+| Latchup Performance | ILatchup | -300 | | 300 | mA | Above VCC and below GND at 85 °C (EIA/JESD78) | 3 |+| Thermal resistance, junction-to-ambient | θJA | | | 112 | °C/W | SOIC package | 3 |+| Power Dissipation in Still Air at 85 °C | PD | | | 500 | mW | SOIC; still air at 85 °C | 3 |+| DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | Referenced to GND | 3 |+| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | | | V | Referenced to GND; upper limit printed as VCC | 3 |+| Operating Temperature, All Package Types | TA | -55 | | 125 | °C | All package types | 3 |+| Input Rise and Fall Time (A or B, Reset) max | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V (Figure 6) | 3 |+| Input Rise and Fall Time max | tr, tf | 0 | | 500 | ns | VCC = 4.5 V (Figure 6) | 3 |+| Input Rise and Fall Time max | tr, tf | 0 | | 400 | ns | VCC = 6.0 V (Figure 6) | 3 |+| External Timing Resistor Rx | Rx | 1 | | | kΩ | VCC < 4.5 V; maximum given by footnote † | 3 |+| External Timing Resistor Rx | Rx | 2 | | | kΩ | VCC ≥ 4.5 V; maximum given by footnote † | 3 |+| External Timing Capacitor Cx | Cx | 0 | | | µF | Maximum given by footnote † | 3 |+| Minimum High-Level Input Voltage | VIH | 1.5 | | | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |+| Minimum High-Level Input Voltage | VIH | 3.15 | | | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |+| Minimum High-Level Input Voltage | VIH | 4.2 | | | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |+| Maximum Low-Level Input Voltage | VIL | | | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |+| Maximum Low-Level Input Voltage | VIL | | | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |+| Maximum Low-Level Input Voltage | VIL | | | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA | 4 |+| Minimum High-Level Output Voltage | VOH | 1.9 | | | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |+| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |+| Minimum High-Level Output Voltage | VOH | 5.9 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |+| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ −4.0 mA; −55 to 125 °C | 4 |+| Minimum High-Level Output Voltage | VOH | 5.2 | | | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ −5.2 mA; −55 to 125 °C | 4 |+| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC = 2.0 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA | 4 |+| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; −55 to 125 °C | 4 |+| Maximum Input Leakage Current (A, B, Reset) | Iin | -1 | | 1 | µA | Vin = VCC or GND; VCC = 6.0 V; −55 to 125 °C | 4 |+| Maximum Input Leakage Current (Rx, Cx) | Iin | -500 | | 500 | nA | Vin = VCC or GND; VCC = 6.0 V; −55 to 125 °C | 4 |+| Maximum Quiescent Supply Current (per package), Standby State | ICC | | | 350 | µA | Vin = VCC or GND; Q1 and Q2 = Low; Iout = 0; VCC = 6.0 V; −55 to 125 °C | 4 |+| Maximum Supply Current (per package), Active State | ICC | | | 800 | µA | Vin = VCC or GND; Q1 and Q2 = High; Iout = 0; Pins 2 and 14 = 0.5 VCC; VCC = 6.0 V; −55 to 125 °C | 4 |+| Maximum Input Capacitance (A, B, Reset) (Cx, Rx) | Cin | | 10 | 25 | pF | −55 to 125 °C | 5 |+| Maximum Propagation Delay Input A or B to Q | tPLH | | | 265 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Input A or B to Q | tPLH | | | 53 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Input A or B to Q | tPLH | | | 45 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Input A or B to NQ | tPHL | | | 295 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Input A or B to NQ | tPHL | | | 59 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Input A or B to NQ | tPHL | | | 50 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Reset to Q | tPHL | | | 265 | ns | VCC = 2.0 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Reset to Q | tPHL | | | 53 | ns | VCC = 4.5 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Maximum Propagation Delay Reset to Q | tPHL | | | 45 | ns | VCC = 6.0 V; CL = 50 pF; tr = tf = 6.0 ns; −55 to 125 °C | 5 |+| Output Pulse Width | τ | 0.59 | | 0.81 | ms | Rx = 10 kΩ, Cx = 0.1 µF, VCC = 5.0 V, CL = 50 pF; −55 to 125 °C | 6 |+| Pulse Width Match Between Circuits in the same Package | | -5 | | 5 | % | Rx = 10 kΩ, Cx = 0.1 µF, CL = 50 pF | 6 |+| Pulse Width Match Variation (Part to Part) | | -10 | | 10 | % | Rx = 10 kΩ, Cx = 0.1 µF, CL = 50 pF; −55 to 125 °C | 6 |++## CAD (KiCad official)++- Symbol: `MC74HC4538ADR2G`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `mc74hc4538adr2g-etched.step` / `mc74hc4538adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc4538adr2g.step` / `mc74hc4538adr2g.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc4538a-d.pdf) (15 pp, sha256 `07efc7703fe04933`, retrieved 2026-11-06, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mc74hc4538adr2g-datasheet.pdf)
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The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. Because the device has conditioned trigger inputs, there are no trigger-input rise and fall time restrictions. The output pulse width is determined by the external timing components, Rx and Cx. The device has a reset function which forces the Q output low and the Q output high, regardless of the state of the output pulse circuitry.</rdf:li>+ </rdf:Alt>+ </dc:description>+ <xmp:CreateDate>2014-08-29T10:41:24+02:00</xmp:CreateDate>+ <xmp:CreatorTool>BroadVision, Inc.</xmp:CreatorTool>+ <xmp:ModifyDate>2020-09-29T10:42:19+02:00</xmp:ModifyDate>+ <xmp:MetadataDate>2020-09-29T10:42:19+02:00</xmp:MetadataDate>+ <pdf:Producer>Acrobat Distiller 9.0.0 (Windows)</pdf:Producer>+ <xmpMM:DocumentID>uuid:10f4707f-b466-4410-95af-9c097abb7186</xmpMM:DocumentID>+ <xmpMM:InstanceID>uuid:ae967d96-1f57-4602-a129-967a19bb6a36</xmpMM:InstanceID>+ <illustrator:StartupProfile>Print</illustrator:StartupProfile>+ </rdf:Description>+ </rdf:RDF>+</x:xmpmeta>+ + + + + + + + + + + + + + + + + + + + + +<?xpacket end="w"?> +endstream+endobj+4 0 obj+<<+/Nums [12 21 0 R 13 22 0 R 14 23 0 R]+>>+endobj+6 0 obj+<<+/Annots [24 0 R]+/Contents [25 0 R 26 0 R 27 0 R 28 0 R 29 0 R 30 0 R 31 0 R 32 0 R]+/CropBox [0.0 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