component
MC74ACT373DTR2G
Public Made by Adomby adom
onsemi Latches, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+206−8@@ -1,13 +1,216 @@ {+ "schema_version": 1,+ "type": "component", "slug": "mc74act373dtr2g",+ "title": "MC74ACT373DTR2G",+ "brief": "onsemi Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "onsemi Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "mc74act373dtr2g" ],+ "component": {+ "mpn": "MC74ACT373DTR2G",+ "manufacturer": "onsemi",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929129677008896",+ "parts": {+ "symbol": "mc74act373dtr2g.kicad_sym",+ "footprint": "mc74act373dtr2g.kicad_mod",+ "model_3d": "mc74act373dtr2g.glb",+ "model_3d_step": "mc74act373dtr2g.step",+ "lbr": "mc74act373dtr2g.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Output Enable, active-LOW. When LOW the O0-O7 latch outputs are driven; when HIGH the outputs are placed in the high-impedance 3-state condition."+ },+ {+ "number": "2",+ "name": "O0",+ "type": "tri_state",+ "description": "3-state latch output bit 0. Reflects D0 while LE is HIGH (transparent) and holds the last latched value when LE goes LOW. Source/sink 24 mA."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "input",+ "description": "Data input bit 0. Latched into the corresponding flip-flop on the HIGH-to-LOW transition of LE (TTL-compatible input on ACT373)."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Data input bit 1. Latched into the corresponding flip-flop on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "5",+ "name": "O1",+ "type": "tri_state",+ "description": "3-state latch output bit 1. Follows D1 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "6",+ "name": "O2",+ "type": "tri_state",+ "description": "3-state latch output bit 2. Follows D2 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "7",+ "name": "D2",+ "type": "input",+ "description": "Data input bit 2. Latched on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "8",+ "name": "D3",+ "type": "input",+ "description": "Data input bit 3. Latched on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "9",+ "name": "O3",+ "type": "tri_state",+ "description": "3-state latch output bit 3. Follows D3 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V) for the device. Connect directly to the system ground plane."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch Enable. When HIGH the latches are transparent (Q follows D); on the HIGH-to-LOW edge the current D0-D7 values are stored and held while LE remains LOW."+ },+ {+ "number": "12",+ "name": "O4",+ "type": "tri_state",+ "description": "3-state latch output bit 4. Follows D4 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "13",+ "name": "D4",+ "type": "input",+ "description": "Data input bit 4. Latched on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "14",+ "name": "D5",+ "type": "input",+ "description": "Data input bit 5. Latched on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "15",+ "name": "O5",+ "type": "tri_state",+ "description": "3-state latch output bit 5. Follows D5 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "16",+ "name": "O6",+ "type": "tri_state",+ "description": "3-state latch output bit 6. Follows D6 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "17",+ "name": "D6",+ "type": "input",+ "description": "Data input bit 6. Latched on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "18",+ "name": "D7",+ "type": "input",+ "description": "Data input bit 7. Latched on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "19",+ "name": "O7",+ "type": "tri_state",+ "description": "3-state latch output bit 7. Follows D7 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply pin. ACT373 operates at 4.5-5.5 V (5 V nominal TTL-compatible operation). Decouple locally with a 0.1 uF capacitor to GND."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929129677008896",+ "pages": null,+ "sha256": "fe8a9d1ee563cf0a",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "onsemi",+ "Package": "TSSOP-20",+ "Category": "Logic",+ "Pins": "20"+ }+ },+ "variants": [+ {+ "mpn": "MC74ACT373DTR2G",+ "kind": "packaging"+ },+ {+ "mpn": "MC74ACT373DTR2GDTG",+ "kind": "packaging"+ },+ {+ "mpn": "MC74ACT373DTR2GDWR2G",+ "kind": "packaging"+ },+ {+ "mpn": "MC74ACT373DTR2GDWG",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "mc74act373dtr2g"+ ],+ "discovery_pitch": "MC74ACT373DTR2G (onsemi) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +228,5 @@ "docs/mc74act373dtr2g-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }